• Journal of IKEEE
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• v.23 no.4
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• pp.1288-1294
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• 2019

The channel-achieving property made the polar code show to advantage as an error-correcting code. However, sufficient error-correction performance shows the asymptotic property that is achieved when the length of the code is long. Therefore, efficient architecture is needed to realize the implementation of very-large-scale integration for the case of long input data. Although the most basic fully parallel encoder is intuitive and easy to implement, it is not suitable for long polar codes because of the high hardware complexity. Complementing this, a partially parallel encoder was proposed which has an excellent result in terms of hardware area. Nevertheless, this method has not been completely generalized and has the disadvantage that different architectures appear depending on the hardware designer. In this paper, we propose a hardware design scheme that applies the proposed systematic approach which is optimized for bit-dimension permutations. By applying this solution, it is possible to design a generalized partially parallel encoder for long polar codes with the same intuitive architecture as a fully parallel encoder.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1985.10a
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• pp.202-205
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• 1985

• Journal of Platform Technology
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• v.6 no.4
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• pp.26-33
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• 2018

In this paper, we propose an image retrieval algorithm for real-time processing and design it as hardware. The proposed method is based on the classification of BoWs(Bag of Words) algorithm and proposes an image search algorithm using bit stream. K-fold cross validation is used for the verification of the algorithm. Data is classified into seven classes, each class has seven images and a total of 49 images are tested. The test has two kinds of accuracy measurement and speed measurement. The accuracy of the image classification was 86.2% for the BoWs algorithm and 83.7% the proposed hardware-accelerated software implementation algorithm, and the BoWs algorithm was 2.5% higher. The image retrieval processing speed of BoWs is 7.89s and our algorithm is 1.55s. Our algorithm is 5.09 times faster than BoWs algorithm. The algorithm is largely divided into software and hardware parts. In the software structure, C-language is used. The Scale Invariant Feature Transform algorithm is used to extract feature points that are invariant to size and rotation from the image. Bit streams are generated from the extracted feature point. In the hardware architecture, the proposed image retrieval algorithm is written in Verilog HDL and designed and verified by FPGA and Design Compiler. The generated bit streams are stored, the clustering step is performed, and a searcher image databases or an input image databases are generated and matched. Using the proposed algorithm, we can improve convenience and satisfaction of the user in terms of speed if we search using database matching method which represents each object.

• Journal of IKEEE
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• v.28 no.1
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• pp.26-32
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• 2024

Recently, various video resolution formats have emerged, and digital devices have built in dedicated scaler chips to support them by enlarging or reducing the resolution of input videos. Therefore, the performance and hardware size of scaler chips are important. In this paper, the combinatorial interpolation scaler algorithm proposed by Han is used to design the hardware using the line memory structure with dual-clock proposed by Han and Jung. The proposed hardware is capable of real-time processing in QHD environments, designed using Verilog, and validated using Xilinx's Vivado 2023.1. We also verify the performance of Han's proposed algorithm with a quantitative numerical evaluation of the proposed hardware.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.3
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• pp.26-31
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• 2009

In this paper, we propose the receiver algorithms suitable for the ECMA standard proposed for multi-gigabit packet transmission in 60 GHz band. In the ECMA standard, various modulation schemes are used for system flexibility. Hence, it is crucial to develop receiver algorithms supporting various modulation schemes with an uniform hardware structure. In this paper, we propose the receiver algorithms supporting DBPSK, DQPSK and OOK modulation schemes simultaneously. The proposed algorithms are not only hardware efficient but also support various modulation schemes with an uniform hardware structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.2
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• pp.171-181
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• 1988

In this study, a packet voice/data terminal(PVDT) that services both voice and data in the packet-switched network is implemented. The software structure of the PVDT is designed according to the OSI 7 layer architecture. The discrimination of voice and data is made in the link layer. Voice packets have priority over data packets in order to minimize the transmission delay, and are serviced by a simple protocol so that the overhead arising form the retransmission of packets may be minimized. The hardware structure of the PVDT is divided into five modules; a master control module, a speech proessing module, a speech activity detection module, a telephone interface module, and an input/output interface module. In addition to the hardware implementation, the optimal reconstruction delay of voice packets to reduce the influence of delay variance is analyzed.

• Wind and Structures
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• v.17 no.6
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• pp.629-646
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• 2013

One of the most common solutions adopted to reduce vibrations of skyscrapers due to wind or earthquake action is to add external damping devices to these structures, such as a TMD (Tuned Mass Damper) or TLCD (Tuned Liquid Column Damper). It is well known that a TLCD device introduces on the structure a nonlinear damping force whose effect decreases when the amplitude of its motion increases. The main objective of this paper is to describe a Hardware-in-the-Loop test able to validate the effectiveness of the TLCD by simulating the real behavior of a tower subjected to the combined action of wind and a TLCD, considering also the nonlinear effects associated with the damping device behavior. Within this test procedure a scaled TLCD physical model represents the hardware component while the building dynamics are reproduced using a numerical model based on a modal approach. Thanks to the Politecnico di Milano wind tunnel, wind forces acting on the building were calculated from the pressure distributions measured on a scale model. In addition, in the first part of the paper, a new method for evaluating the dissipating characteristics of a TLCD based on an energy approach is presented. This new methodology allows direct linking of the TLCD to be directly linked to the increased damping acting on the structure, facilitating the preliminary design of these devices.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.163-170
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• 2007

In this paper, we propose that the polyphase scaler whose performance to that of the bicubic method, has less complexity in hardware structure. In order to get the new information, proposed system is based on the group delay which is one of the digital filter characteristics. The performance of this system is superior to that of bicubic algorithm which is well known. Because the hardware structure is simpler than other image scalers, we can adopt this system for mobile devices easily. The previous polyphase filters make blurring noise which is generated by up-scaling. We replace polyphase filters by boost-up filter to get vivid image. The proposed scaler is verified by Xilinx Virtex2 FPGA and is used as digital Boom in mobile camera phone.

• Journal of Communications and Networks
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• v.13 no.1
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• pp.70-76
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• 2011

This paper presents the unified user equipment (UE) baseband modulation and demodulation (modem) hardware platform architecture to support multiple radio access technologies. In particular, this platform selectively supports two systems; one is HEDGE system, which is the combination of third generation partnership project (3GPP) Release 7 high speed packet access evolution (HSPA+) and global system for mobile communication (GSM)/general packet radio service (GPRS)/enhanced data rates for GSM evolution (EDGE), while the other is LEDGE system, which is the combination of 3GPP Release 8 long term evolution (LTE) and GSM/GPRS/EDGE. This is done by applying the flexible pin multiplexing scheme to a hardwired pin mapping process. On the other hand, to provide stable connection, high portability, and high debugging ability, the stacking structure is employed. Here, a layered board architecture grouped by functional classifications is applied instead of the conventional one flatten board. Based on this proposed configuration, we provide a framework for the verification step in wireless cellular communications. Also, modem function/scenario test and inter-operability test with various base station equipments are verified by system requirements and scenarios.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3031-3033
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• 2005

High speed PC-based digital I/O system hardware, PCI-bus master and slave set is developed, which features are distributed structure, input/output function interchangeability by switch setting, high speed 20Mbps to update 1000 points in less than 1 ms, etc.