Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Hardware Design for Real-Time Processing of a Combinatorial Interpolation Scaler with Asymmetric Down-scaling and Up-scaling

비대칭 축소 및 확대가 가능한 조합 보간 알고리즘의 실시간 처리를 위한 하드웨어 설계

  • Si-Yeon Han (Dept. of Electronics Engineering, Dong-A University) ;
  • Semin Jung (Dept. of Electronics Engineering, Dong-A University) ;
  • Jeong-Hyeon Son (Dept. of Electronics Engineering, Dong-A University) ;
  • Jae-Seong Lee (Dept. of Electronics Engineering, Dong-A University) ;
  • Bong-Soon Kang (Dept. of Electronics Engineering, Dong-A University)
  • Received : 2024.02.26
  • Accepted : 2024.03.15
  • Published : 2024.03.31
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Abstract

Recently, various video resolution formats have emerged, and digital devices have built in dedicated scaler chips to support them by enlarging or reducing the resolution of input videos. Therefore, the performance and hardware size of scaler chips are important. In this paper, the combinatorial interpolation scaler algorithm proposed by Han is used to design the hardware using the line memory structure with dual-clock proposed by Han and Jung. The proposed hardware is capable of real-time processing in QHD environments, designed using Verilog, and validated using Xilinx's Vivado 2023.1. We also verify the performance of Han's proposed algorithm with a quantitative numerical evaluation of the proposed hardware.

최근 다양한 영상의 해상도 포맷이 등장하였고, 디지털 기기는 이를 지원하기 위해 입력 영상의 해상도를 확대 또는 축소하는 전용 스케일러 칩을 내장하고 있다. 따라서 스케일러 칩의 성능과 하드웨어 크기는 중요하다고 할 수 있다. 본 논문에서는 Han이 제안한 조합 보간 스케일러 알고리즘을 Han, Jung이 제안한 Dual-clock을 가지는 라인 메모리 구조를 이용해 하드웨어 설계를 진행하였다. 제안하는 하드웨어는 QHD 환경에서 실시간으로 처리가 가능한 구조로, Verilog를 이용해 설계되었으며 Xilinx Vivado 2023.1을 이용하여 검증하였다. 또한 Han이 제안한 알고리즘과 하드웨어의 정량적 수치 평가 비교를 통해 성능을 검증하였다.

Keywords

Acknowledgement

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. NRF-2023R1A2C1004592)

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