• Journal of IKEEE
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• v.27 no.3
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• pp.296-302
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• 2023

As Multimedia industry has evolved, it has become possible to display resolutions in various formats. Therefore, the performance of a scaler algorithm that converts resolutions while maintaining high quality and its hardware implementation are important. Considering the hardware design of an image up/down scaler, this paper proposes a combinatorial scaler algorithm that uses modified bilinear interpolation in the vertical direction and bicubic interpolation in the horizontal direction to reduce the line memory burden. Through quantitative and qualitative evaluations, this paper compared the performance of the proposed algorithm with three other well-known algorithms, and also compared the hardware burden of its hardware implementation. This paper used a sinusoidal signal and eight typical images for performance evaluation.

• Journal of IKEEE
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• v.28 no.1
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• pp.26-32
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• 2024

Recently, various video resolution formats have emerged, and digital devices have built in dedicated scaler chips to support them by enlarging or reducing the resolution of input videos. Therefore, the performance and hardware size of scaler chips are important. In this paper, the combinatorial interpolation scaler algorithm proposed by Han is used to design the hardware using the line memory structure with dual-clock proposed by Han and Jung. The proposed hardware is capable of real-time processing in QHD environments, designed using Verilog, and validated using Xilinx's Vivado 2023.1. We also verify the performance of Han's proposed algorithm with a quantitative numerical evaluation of the proposed hardware.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.163-170
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• 2007

In this paper, we propose that the polyphase scaler whose performance to that of the bicubic method, has less complexity in hardware structure. In order to get the new information, proposed system is based on the group delay which is one of the digital filter characteristics. The performance of this system is superior to that of bicubic algorithm which is well known. Because the hardware structure is simpler than other image scalers, we can adopt this system for mobile devices easily. The previous polyphase filters make blurring noise which is generated by up-scaling. We replace polyphase filters by boost-up filter to get vivid image. The proposed scaler is verified by Xilinx Virtex2 FPGA and is used as digital Boom in mobile camera phone.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.22-34
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• 2010

Existing image scalers generally adopt simple interpolation methods such as bilinear method to take cost-benefit, or highly complex architectures to achieve high quality resulting images. However, demands for a low power, low cost, and high performance image scaler become more important because of emerging high quality mobile contents. In this paper we propose the novel low power hardware architecture for a high quality raster scan image scaler. The proposed scaler architecture enhances the existing cubic interpolation look-up table architecture by reducing and optimizing memory access and hardware components. The input data buffer of existing image scaler is replaced with line memories to reduce the number of memory access that is critical to power consumption. The cubic interpolation formula used in existing look-up table architecture is also rearranged to reduce the number of the multipliers and look-up table size. Finally we analyze the optimized parameter sets of look-up table, which is a trade-off between quality of result image and hardware size.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1895-1900
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• 2010

In this paper, we propose the hardware architecture of a display converter which is consisted of four functional blocks. The four functional blocks consists of a set of color space converter, de-interacer, video display scaler, and gamma corrector. After the proposed architecture was implemented into hardware, we verified that it operated exactly. The designed hardware has 7,629 LUT and 6,800 Logic Register in Stratix device of Altera and operates in 270 MHz clock frequency.

• ETRI Journal
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• v.42 no.4
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• pp.596-607
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• 2020

Scaling is an important operation because of the iterative nature of arithmetic processes in digital signal processors (DSPs). In residue number system (RNS)-based DSPs, scaling represents a performance bottleneck based on the complexity of intermodulo operations. To design an efficient RNS scaler for special moduli sets, a body of literature has been dedicated to the study of the well-known moduli sets {2ⁿ - 1, 2ⁿ, 2ⁿ + 1} and {2ⁿ, 2ⁿ - 1, 2ⁿ⁺¹ - 1}, and their extension in vertical or horizontal forms. In this study, we propose an efficient programmable RNS scaler for the arithmetic-friendly moduli set {2^n+p, 2ⁿ - 1, 2ⁿ⁺¹ - 1}. The proposed algorithm yields high speed and energy-efficient realization of an RNS programmable scaler based on the effective exploitation of the mixed-radix representation, parallelism, and a hardware sharing technique. Experimental results obtained for a 130 nm CMOS ASIC technology demonstrate the superiority of the proposed programmable scaler compared to the only available and highly effective hybrid programmable scaler for an identical moduli set. The proposed scaler provides 43.28% less power consumption, 33.27% faster execution, and 28.55% more area saving on average compared to the hybrid programmable scaler.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.11
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• pp.3094-3097
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• 2009

The use of general-purpose divider is inevitable to implement a image down-scaler when an arbitrary scaling ratio is given. To get an output at every clock from the divider, the divider should be implemented by LUT, however, its hardware size will be bigger and bigger as the precision level is increased. In this paper, a new image scaling algorithm is presented for a arbitrary scaling ratio, which do not requires a general-purpose or LUT-based divider. The proposed algorithm utilizes only comparators and adders such that the hardware size can be reduced by 1/10 compared to the conventional approaches.

• Journal of the Korea Society of Computer and Information
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• v.26 no.8
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• pp.1-11
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• 2021

This paper proposes a novel mechanism called Event-driven Uncore Frequency Scaler (eUFS) to improve the energy efficiency of the HPC systems. UFS exploits the hardware events such as LAPI (Last-level Cache Accesses Per Instructions) and CPI (Clock Cycles Per Instruction) to dynamically adjusts the uncore frequency. Hardware events are collected at a reference time period, and the target uncore frequency is determined using the collected event and the previous uncore frequency. Experiments with the NPB benchmarks demonstrate that the eUFS reduces the energy consumption by 6% on average for class C and D NPB benchmarks while it only increases the execution time by 2% on average.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.

• 한국HCI학회:학술대회논문집
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• 2009.02a
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• pp.615-619
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• 2009

A real-time, continuous-scale image interpolation method is proposed based on bi-linear interpolation with directionally adaptive low-pass filtering. The proposed algorithm has been optimized for hardware implementation. The original bi-linear interpolation method has blocking artifact. The proposed algorithm solves this problem using directionally adaptive low-pass filtering. It can also solve the severely problem by selection choosing low-pass filter coefficients. Therefore the proposed interpolation algorithm can realize a high-quality image scaler for various imaging systems, such as digital camera, CCTV and digital flat panel display, to name a few.