• Journal of Korea Multimedia Society
• /
• v.2 no.4
• /
• pp.476-489
• /
• 1999

HW/SW codesign is integrated design of systems implemented using both hardware and software components. Many design tools has been developed to support this new paradigm, so far. Current codesign tools are not widely used as been expected because of variety problems - rapidly evolving technology, platform dependency, absence of standard specification method, inconsistent user interface, varying target system, different functionality In this paper, we propose a web-based distributed HW/SW codesign environment to remedy this kinds of problem. Our codesign environment has object-based 3 tier client/server architecture. It supports collaborative workspace through session service. Fully object-oriented design of user interface(OOUI) enables easy extension without change of user Interface. Furthermore it contains transaction server and security server for efficient and safe transfer of design data. To show a validity of our design, we developed prototype of web-based HW/SW codesign environment called WebCEDA. Our model of HW/SW codesign can be used for web-based generic CAD tools.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.120-123
• /
• 2000

In this paper, A target architecture and interface synthesizer are proposed for processor-embedded codesign. The target architecture has the form of ARM processor based on AMBA. The interface synthesizer automatically generates an interface circuit for the communication between HW and SW. A memory map is used as the communication channel and an interrupt-based interface is applied for synchronized communication between HW and SW modules. In order to verify the function and performance of proposed target architecture and the interface synthesizer, practical test example is applied. Experimental results show the proposed interface synthesizer functioned correctly in the HW/SW codesign environment.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2004.11a
• /
• pp.203-206
• /
• 2004

본 논문은 SoC 환경에서 암호화 알고리즘의 처리 성능을 향상시키기 위해 각 노드의 실행 시간을 비교하여 하드웨어와 소프트웨어로 codesign 하였다. 암호화 알고리즘으로서는 DES와 SHA-1을 통합 설계하여 적용하였다. 본 논문에서의 codesign 방법을 altera의 excalibur에서 구현하여 실행 시간 및 메모리 크기 그리고 회로의 게이트 크기를 비교 대상으로 하였다. 수행 결과에 따른 분석에 의하면 세가지 비교 대상에 최적화하여 codesign 성능을 찾을 수 있었다.

• Journal of Korea Multimedia Society
• /
• v.3 no.6
• /
• pp.661-673
• /
• 2000

In this paper, we propose a Web-based HW/SW Codesign Environment with Distributed Architecture (WebCEDA), then design and implement SpecCharts Specification Environment(ScSE) for specifying systems in WebCEDA. WebCEDA has 3-tier client/server architecture than can remedy disadvantages of existing codesign tools, such as platform dependency, difficulty of extension, absence of collaboraton environment. ScSE includes web interface, SpecCharts editor, HW/SW codesin application sever and SpecCharts translator. To verify the operation of ScSE, we specify several example system using SpecCharts editor, then translate it to VHDL using SpecCharts translator and simulate the translated VHDL codes on synopsys. As the results, we know that ScSE has correct operations, also obtain the following advantages, the reduction in system complexity and the natural abstract design.

• Proceedings of the Korean Information Science Society Conference
• /
• 2006.06c
• /
• pp.178-180
• /
• 2006

임베디드 시스템이 복잡해지고 Time-to-Market이 요구되면서 HW/SW 통합설계 방법론(codesign)이 제시되었다. 통합설계 과정 중, HW/SW 분할 과정은 시간 성능, 비용, 전력 등의 모든 요구사항을 만족시키기는 불가능하므로 특정 목적함수에 근거한 알고리즘을 이용하여 진행된다. 하지만 고정된 분할 알고리즘을 이용해서는 이해관계자들의 요구사항을 최대한 반영하기 어렵다. 본 논문에서는 이해관계자들의 의견을 최대한 반영하고, 이를 만족시키는 모델을 유도하기 위하여 WinWin negotiation model을 적용된 요구사항 절충을 고려한 HW/SW 분할 방법론을 제안하였다. WinWin 모델을 통해서 도출된 요구사항에 가장 적합한 목적함수를 가지는 분할 알고리즘을 선택하여 HW/SW 분할 과정을 진행하는 방법이다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.05a
• /
• pp.641-642
• /
• 2011

This paper presents method of constructing the embedded systems based on hardware-software codesign which is the important fields of $21^{st}$ information technology. First, we describe the classification and necessity of embedded systems, and we discuss the consideration and classification for constructing the embedded systems. Also, we discuss the embedded systems modeling. The proposed embedded systems based on hardware-software co-design is important gradually, we expect that it involve the many IT fields in the future.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.419-420
• /
• 2000

This paper describes the innovation of VLSI design methodology in the coming decade. Technology trend of VLSI fabrication is surveyed first. Then the so-called “design crisis” is analyzed. Finally, possible design methodology to overcome the design crisis is discussed.

• Journal of information and communication convergence engineering
• /
• v.6 no.4
• /
• pp.376-382
• /
• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.5
• /
• pp.232-242
• /
• 2005

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in BFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.

• Journal of KIISE:Computer Systems and Theory
• /
• v.34 no.8
• /
• pp.337-347
• /
• 2007

An embedded system is called a multi-mode embedded system if it performs multiple applications by dynamically reconfiguring the system functionality. Further, the embedded system is called a multi-mode multi-task embedded system if it additionally supports multiple tasks to be executed in a mode. In this Paper, we address a HW/SW partitioning problem, that is, HW/SW partitioning of multi-mode multi-task embedded applications with timing constraints of tasks. The objective of the optimization problem is to find a minimal total system cost of allocation/mapping of processing resources to functional modules in tasks together with a schedule that satisfies the timing constraints. The key success of solving the problem is closely related to the degree of the amount of utilization of the potential parallelism among the executions of modules. However, due to an inherently excessively large search space of the parallelism, and to make the task of schedulabilty analysis easy, the prior HW/SW partitioning methods have not been able to fully exploit the potential parallel execution of modules. To overcome the limitation, we propose a set of comprehensive HW/SW partitioning techniques which solve the three subproblems of the partitioning problem simultaneously: (1) allocation of processing resources, (2) mapping the processing resources to the modules in tasks, and (3) determining an execution schedule of modules. Specifically, based on a precise measurement on the parallel execution and schedulability of modules, we develop a stepwise refinement partitioning technique for single-mode multi-task applications. The proposed techniques is then extended to solve the HW/SW partitioning problem of multi-mode multi-task applications. From experiments with a set of real-life applications, it is shown that the proposed techniques are able to reduce the implementation cost by 19.0% and 17.0% for single- and multi-mode multi-task applications over that by the conventional method, respectively.