Journal of KIISE:Computer Systems and Theory (한국정보과학회논문지:시스템및이론)

Korean Institute of Information Scientists and Engineers (한국정보과학회)
권호 표지

Hardware Synthesis From Coarse-Grained Dataflow Specification For Fast HW/SW Cosynthesis

빠른 하드웨어/소프트웨어 통합합성을 위한 데이타플로우 명세로부터의 하드웨어 합성

  • 정현욱 (서울대학교 전기컴퓨터공학부) ;
  • 하순회 (서울대학교 전기컴퓨터공학부)
  • Published : 2005.06.01
Download PDF
⟨ Previous Next ⟩

Abstract

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in BFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.

이 논문에서는 빠른 하드웨어/소프트웨어 통합합성을 위해 데이타플로우 그래프(DFG: Dataflow Graph)로부터 하드웨어를 자동으로 합성하는 내용을 다룬다. 이 데이타플로우 그래프에서 로드는 FIR(Finite Impulse Response) 필터나 DCT(Discrete Cosine Transform) 블록과 같이 크기가 어느 정도 되는 하드웨어 블록을 나타내며, 이 노드의 포트는 한번 수행할 때마다 하나 이상의 데이타 샘플을 주고 받을 수 있다. 즉, 멀티레이트 데이타 샘플(multi-rate data sample)을 교환한다. 이러한 특성들은 기존의 Behavioral Synthesis와 구별되는 점이며, 따라서 Behavioral Synthesis보다 어려운 문제가 된다. 본 논문에서 제안하는 설계 방법을 사용하면 알고리즘을 명세하는 데이타플로우 그래프는 하드웨어 리소스의 할당과 스케줄 정보에 따라 다양한 하드웨어 구조로 매핑될 수 있다. 따라서 하드웨어 설계시에 면적/성능 트레이드오프 관계를 손쉽게 관리할 수 있으며, 하드웨어를 자동으로 합성하는 기존의 방식보다구현 가능한 하드웨어 설계 공간을 더욱 넓혀주는 효과를 거둘 수 있다.

Keywords

References

  1. Synopsys Inc., 700 E. Middlefield Rd., Mountain View, CA 94043, USA. COSSAP User's Manual: VHDL Code Generation
  2. J. T. Buck, S. Ha, E. A. Lee and D. G. Messerschmitt. Ptolemy: A framework for simulating and prototyping heterogeneous systems. Int'l journal of Computer simulation, special issues on 'Simulation software development,' vol.4, pp. 155-182, April, 1994
  3. M. Ade, R. Lauwereins, and J. A. Peperstraete. Hardware-software codesign with GRAPE. IEEE Int'l Workshop on Rapid System Prototyping, pp. 40-47, June, 1995 https://doi.org/10.1109/IWRSP.1995.518569
  4. G. De Micheli. Synthesis and Optimization of Digital Circuits. New York, McGraw-Hill, Inc., 1994
  5. E. A. Lee and D. G. Messerschmitt. Synchronous data flow. Proc. of the IEEE, September, 1987
  6. H. Oh and S. Ha. Fractional rate dataflow model and efficient code synthesis for multimedia applications. ACM SIGPLAN Notice Vol. 37, pp. 12-17, July 2002 https://doi.org/10.1145/566225.513834
  7. H. Oh and S. Ha. Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints. International Workshop on Hardware/Software Codesign, pp. 133-138, May 2002 https://doi.org/10.1145/774789.774817
  8. P. Zepter and T. Groker and H. Meyr, Digital receiver design using VHDL generation from data flow graphs. Proceedings of the Design Automation Conference 1995 https://doi.org/10.1109/DAC.1995.250095
  9. J. Horstmannshoff and H. Meyr. Optimized system synthesis of complex RT level building blocks from multirate dataflow graphs. International Symposium on System Synthesis, pp. 38-43, Nov, 1999 https://doi.org/10.1109/ISSS.1999.814258
  10. M. C. Williamson and E. A. Lee. Synthesis of parallel hardware implementations from synchronous dataflow graph specifications. In 30th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 1996 https://doi.org/10.1109/ACSSC.1996.599166
  11. Y.-L. Lin. Recent Devleopments in High-Level Synthesis. ACM Transactions on Design Automation of Electronic Systems, Vol. 2, No.1, pp 2-21, Jan. 1997 https://doi.org/10.1145/250243.250245
  12. D. W. Knapp. Behavioral Synthesis: Digital System Design Using the Synopsys Behavioral Compiler. Prentice Hall, 1996
  13. L. Semeria, K. Sato, and G. De Micheli. Synthesis of Hardware Models in C With Pointers and Complex Data Structures. IEEE Transactions on VLSI Systems Vol. 9, pp. 743-756, Dec. 2001 https://doi.org/10.1109/92.974889
  14. L. Semeria and G. De Micheli. Resolution, Optimization, and Encoding of Pointer Variables for the Behavioral Synthesis from C. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems Vol. 20, pp. 213-233, Feb. 2001 https://doi.org/10.1109/43.908442
  15. N. Vanspauwen, E. Barros, S. Cavalcante, and C. Valderrama. On the Importance, Problems and Solutions of Pointer Synthesis. 15th Symposium on Integrated Circuits and Systems Design, pp. 317-322, Sept. 2002 https://doi.org/10.1109/SBCCI.2002.1137677
  16. F. Slomka, M. Dorfel, and R. Munzenberger. Generating Mixed Hardware/Software systems from SDL Specifications. $9^{th}$ International Symposium on Hardware/Software Codesign, pp. 116-121, April 2001 https://doi.org/10.1109/HSC.2001.924661
  17. O. Bringmann, W. Rosenstiel, A. Muth, G. Farber, F. Slomka, and R. Hofmann. Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping. IEEE Int'l Workshop on Rapid System Prototyping, pp. 114-119, June 1999 https://doi.org/10.1109/IWRSP.1999.779040
  18. J. Horstmannshoff, T. Grotker. and H. Meyr. Mapping multi-rate dataflow to complex RT level hardware models. In ASAP. IEEE, 1997
  19. J. Dalcolmo, R. Lauwereins, M. Ade. Code generation of data dominated DSP applications for FPGA targets. IEEE Int'l Workshop on Rapid System Prototyping, pp. 162-167, 1998 https://doi.org/10.1109/IWRSP.1998.676686
  20. G. Bilsen, M.Engels, R. Lauwereins and J. Peperstraete. Cycle-static dataflow. IEEE Transactions on Signal Processing Vol. 44, pp.397-408, Feb. 1996 https://doi.org/10.1109/78.485935
  21. H. Jung, K. Lee, and S. Ha. Efficient hardware controller synthesis for synchronous dataflow graph in system level design. IEEE Transactions on VLSI Systems Vol. 10, pp. 423-428, August 2002 https://doi.org/10.1109/TVLSI.2002.807765