• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.59-70
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• 2007

In this paper, we proposed an effective T&L(Transform & Lighting) Processor architecture for a real time 3D graphics acceleration SoC(System on a Chip) in a mobile system. We designed Floating point arithmetic IPs for a T&L processor. And we verified IPs using a SoC Platform. Designed T&L Processor consists of 24 bit floating point data format and 16 bit fixed point data format, and supports the pipeline keeping the balance between Transform process and Lighting process using a parallel computation of 3D graphics. The delay of pipeline processing only Transform operation is almost same as the delay processing both Transform operation and Lighting operation. Designed T&L Processor is implemented and verified using a SoC Platform. The T&L Processor operates at 80MHz frequency in Xilinx-Virtex4 FPGA. The processing speed is measured at the rate of 20M Vertexes/sec.

• Journal of Korea Multimedia Society
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• v.11 no.6
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• pp.816-827
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• 2008

In this paper, two-stage pipelined floating-point arithmetic unit (FP-AU) is designed. The FP-AU processor supports seventeen operations to apply 3D graphics processor and has area-efficient and low-latency architecture that makes use of modified dual-path computation scheme, new normalization circuit, and modified compound adder based on flagged prefix adder. The FP-AU has about 4-ns delay time at logic synthesis condition using $0.18{\mu}m$ CMOS standard cell library and consists of about 5,930 gates. Because it has 250 MFLOPS execution rate and supports saturated arithmetic including a number of graphics-oriented operations, it is applicable to mobile 3D graphics accelerator efficiently.

• Proceedings of the Korean Society of Computer Information Conference
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• 2008.06a
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• pp.251-255
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• 2008

최근 모바일 시스템의 성능이 향상되면서 다양한 형태의 동적인 메뉴 구성과, 메일 및 이차원 지도 등의 표현에 벡터 그래픽을 도입하고 있다. 모바일 기기에서 사용되는 벡터 그래픽 처리 기술은 Flash Lite, SVG(Scalable Vector Graphics)등이 널리 사용되고 있는데 두 가지 모두 소프트웨어 방식으로 사용되고 있다. 매크로미디어사의 Flash Lite는 연산에 많은 메모리를 필요로 하고, SVG는 웹 표준에 맞춘 스크립트 해석 기반으로 구동 속도가 느리다. 모바일 컴퓨팅 환경에서 벡터 그래픽스에 대한 필요성과 사용빈도가 증가함에 따라 메모리를 적게 사용하고 하드웨어 가속기를 지원 할 수 있도록 저 수준의 API(Application Programming Interface)인 OpenVG 1.0을 크로노스 그룹(Khronos Group)에서 제정하였다. 본 논문은 모바일 사용 환경에 맞추어 사용될 수 있도록 OpenVG 1.0에 기반한 API를 구현하고 실험하였다. 구현된 API는 느린 소프트웨어의 한계를 벗어나기 위해 하드웨어 가속기 설계에 적합하도록 각각의 API 블록 및 형태를 하드웨어 파이프라인 형태의 관점에서 설계하였고, 구현된 API를 윈도우즈 환경에서 기능을 검증하였다.

• Journal of Korea Game Society
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• v.4 no.3
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• pp.65-70
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• 2004

The conventional 3D graphic accelerator is mainly focused on high performance in the application area of computer graphic and 3D video game How ever the existing 3D architecture is not suitable for portable devices because of its huge power. So, we analyze the embedded 3D graphics renderer. After the analyzing, to reduce the power, triangle set-up stage and edge walking stage are executed sequentially while scan-line processing stage and span processing stage which control performance of 3D graphic accelerator are executed parallel.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.917-920
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• 2005

This paper presents 3D graphics geometry processor for mobile applications. Geometry stage needs to cope with the large amount of computation. Geometry stage consists of transformation process and lighting process. To deal with computation in geometry stage, the vector processor that is based on pipeline chaining is proposed. The performance of proposed 3D graphics geometry processor is up to 4.3M vertex/sec at 100 MHz. Also, the designed processor is compliant with OpenGL ES that is widely used for standard API of embedded system. The proposed structure can be efficiently used in 3D graphics accelerator for mobile applications.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.1
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• pp.1-9
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• 1993

In recent days high perfermance graphic operation is needed, since computer graphics is widely used for computer-aided design and simulator using high resolution graphic card. In this paper a graphic accelerator is designd with the functions of graphic primitives generation and geometrical transformations. 1-D Systolic Array Processor for Matris Vector operation is designed and used in main ALU of a graphic accelerator, since these graphic algorithms have comonon operation of Matris Vector. Conclusively, in case that the resolution of graphic domain is 800$\times$600, and 33.3nsec operator is used in a graphic accelerator, 29732 lines per second and approximately 6244 circles per second is generated.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1129-1132
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• 1998

This paper presents a design of special hardware developed for enhancing the floating-point power operations which are actively used at the lighting stage to calculate the specular term in 3D graphics geometry engines. The power operation takes just 4 cycles in our floating-point multiplier while it takes about 100-200 cycles in conventional floating-point units. Although an approximation algorithm is employed in the power operation to reduce the hardware complexity required, the error of power value from the developed floatingpoint multiplier is so minimal that no difference can be found by human eyes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.337-340
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• 2009

Since a hardware accelerator for 3D graphics processing GPU(Graphics Processing Unit)'s performance has been improving constantly. This is the efficient way was introduced for complex graphics application, but it is rarely used to utilize 100% resources on GPU. GP-GPU(general-purpose GPU), including operations on the GPU and supporting common operations can be handled by the processor, is noted by depending on the distribution of resources that can be effectively controlled. In this paper, the simulator was implemented that supports virtual environment of GP-GPU and available for program design and debugging. Through this, the co-design development environment support simultaneous design fast and reliable verification that are available to build the interface of three-dimensional graphics display.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.57-64
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• 2007

This paper proposed the low power texture cache for mobile 3D graphics accelerators. It is very important to reduce the leakage power in the standby mode for mobile 3D graphics accelerators and the memory access latency of texture mapping in the active mode which needs a large memory bandwidth. The proposed structure reduces the leakage power using variable threshold values of power mode transitions according to the selected texture filtering algorithms of application programs, which has the run time gain for texture mapping. In the trace driven cache simulation the proposed structure shows the best 7% performance gain to the previous MSA cache according to the new performance metric considering both normalized leakage power and run time impact.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.89-96
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• 2007

In this paper, we designed 3D graphics rasterizer with a culling and clipping for the efficient 3D graphics accelerator. The proposed rasterizer is implemented for the mobile system and process frustum culling, back face culling, Y-axis clipping and X-axis clipping. The rasterzier consists of triangle setup, edge walk and span process unit. Each unit of rasterzier is designed with a culling and clipping. It supports goraud shading with 16 bits depth values and 16 bits color values. The estimated performance of proposed rasterizer is 52M pixels per second.