• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.289-293
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• 2008

In this paper, we propose the hardware architecture to accelerate 2D Vector graphics process for mobile devices. we propose the Transformation Unit Architecture that considerates the operation dependency. It has 3 cycles excution time and uses 2 multipliers and 2 adders. Proposed paint generation unit uses a LUT method, so it does not execute color interpolation which needs to be calculated every time. The proposed OpenVG 1.0 Accelerator achieved a 2.85 times faster performance in a tiger model.

• Journal of IKEEE
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• v.12 no.2
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• pp.124-130
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• 2008

Vector Graphics describes an image with mathematical statements instead of pixel information. Which enables easy scalability without loss in image quality and usually results in a much smaller file size compared with bitmap images. In this paper, we propose Vector Graphics Accelerator for mobile device with scan-line edge flag algorithm to render vector image without sorting process of edge. Proposed Vector Graphics Accelerator was verified with OpenVG 2D Vector image. The estimated processing time of proposed Accelerator with Tiger image is 12ms on Tessellation process, and total rendering time is 208ms. Estimated rendering performance with Tiger image is about 5 frame per second

• Journal of Korea Multimedia Society
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• v.11 no.10
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• pp.1460-1470
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• 2008

As the performance of recent mobile systems increases, a vector graphic has been implemented to represent various types of dynamic menus, mails, and two-dimensional maps. This paper proposes a hardware accelerator for open vector graphics (OpenVG), which is widely used for two-dimensional vector graphics. We analyze the specifications of an OpenVG and divide the OpenVG into several functions suitable for hardware implementation. The proposed hardware accelerator is implemented on a field programmable gate array (FPGA) board using hardware description language (HDL) and is about four times faster than an Alex processor.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.357-360
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• 2002

This paper is proposed about an efficient pipelined architecture for 3D graphics accelerator to reduce Cache miss ratio. Because cache miss takes a considerable time, about 20∼30 cycle, we reduce cache miss ratio to use pre-fetch. As a result of simulation, we figure out that the miss ratio of cache depends on the size of tile, cache memory and auxiliary cache memory. We can save 6.6% cache miss ratio maximumly.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.5
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• pp.398-406
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• 1991

This paper presents a graphics accelerator for fast image generation. The accelarator has three major functional blocks: linear interpolator, multipliers and Edgee Painting Tree. Linear interpolator with coupled binary tree structure interpolates functional values of two end points. Two multipliers compute input values of interpolator in parallel. Mask pattern which removes out invalid data is generated by Edge Painting Tree. The proposed architecture in this paper is responsible for 64 pixels and can process about 5,900 10x10polygons per second.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.298-301
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• 2008

Vector Graphics describes an image with mathematical statements instead of pixel information, Which enables easy scalability without loss in image quality and usually results in a much smaller file size compared with bitmap images. In this paper, we propose Vector Graphics Rasterizer for mobile device with scan-line edge flag algorithm. Proposed Vector Graphics Accelerator was verified with OpenVG 2D Vector image. The estimated performance of proposed Accelerator is 5 frame per second with Tiger image.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.5
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• pp.97-103
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• 2010

There are many algorithms for 2D to 3D graphic conversion technology which have the high complexity and large scale of iterative computation. So in this paper propose parallel algorithm and high speed graphics accelerator architecture using Park's MAMS(Multiple Access Memory System) for Phong Shading, one of many 3D algorithms. The Proposed SIMD processor architecture is simulated by HDL and simulated and got 30 times faster result. It means any kinds of 3D algorithm can make parallel algorithm and accelerated by SIMD processor with Park's MAMS for real time processing.

• Journal of Korea Game Society
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• v.6 no.4
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• pp.63-70
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• 2006

This paper studied various low power structures of texture caches for mobile 3D graphics accelerator to reduce the memory latency of texture data. Also the paper designed the texture cache with the variable threshold values of power mode transition according to the filtering algorithms. In the trace driven simulation, we compared the performance of those structures using Quake game engine as the benchmark. Also the algorithm was proposed and verified by the simulation, which has variable threshold values of power mode transitions according to the selected texture filtering method.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.761-762
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• 2008

This paper presents a hardware accelerator for accelerating vector graphics applications based on the OpenVG standard. Since our design mainly targets embedded applications, we focus on efficient uses of limited resources, especially the memory bandwidth. The designed accelerator can process the images of $640{\times}240$ pixels with moderate complexity at the rate of 30 frames per second.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.285-288
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• 2008

Most of multimedia processors for 2D/3D graphics acceleration use a lot of integer/floating point arithmetic units. We present a new architecture with an efficient ALU, built in a smaller chip size. It reduces instruction cycles significantly based on a foundation of multi-thread operation, variable length instruction words, dual phase operation, and phase instruction's coordination. We can decrease the number of instruction cycles up to 50%, and can achieve twice better performance.