• KSII Transactions on Internet and Information Systems (TIIS)
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• 제15권7호
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• pp.2339-2355
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• 2021

In this paper, a joint probabilistic data association algorithm based on loss function (LJPDA) is proposed so that the computation load and accuracy of the multi-target tracking algorithm can be guaranteed simultaneously. Firstly, data association is divided in to three cases based on the relationship among validation gates and the number of measurements in the overlapping area for validation gates. Also the contribution coefficient is employed for evaluating the contribution of a measurement to a target, and the loss function, which reflects the cost of the new proposed data association algorithm, is defined. Moreover, the equation set of optimal contribution coefficient is given by minimizing the loss function, and the optimal contribution coefficient can be attained by using the Newton-Raphson method. In this way, the weighted value of each target can be achieved, and the data association among measurements and tracks can be realized. Finally, we compare performances of LJPDA proposed and joint probabilistic data association (JPDA) algorithm via numerical simulations, and much attention is paid on real-time performance and estimation error. Theoretical analysis and experimental results reveal that the LJPDA algorithm proposed exhibits small estimation error and low computation complexity.

• Restorative Dentistry and Endodontics
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• 제20권2호
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• pp.758-767
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• 1995

The purpose of this study was to evaluate canal shaping ability after canal preparation by using engine-driven nickel-titanium file and endosonic file in curved canals. 30 mesiobuccal canals of molars extracted within recent 3 months were divided into 3 groups. Group I and group II were prepared by using engine-driven nickel-titanium Gates-Glidden drill type and the engine-driven nickel-titanium file type. Group III prepared by using en do sonic file. The image of preinstrumented canals was taken by X-ray. The image of postinstrumented canal was taken by X-ray in the same condition of preinstrumentation. A magnified X-ray image on magnifier screen was traced and then compared the preinstrumentated canal image with the postinstrumentated canal image by superimposing method. The following results were obtained : 1. In the change of canal curvature, the engine-driven nickel-titanium Gates-Glidden drill type showed the least change and the ultrasonically filing showed the greatest change. 2. In the percentage of canal enlargement, the engine-driven nickel-titanium file type was greatest at all level(p<0.05), the apex of all group was the greatest, the difference of ultrasonically filing group showed greater between apex and cervix. 3. The percentage of canal enlargement on convex side was greater than that of on concave side in apex of each group(p<0.05). In the ultrasonically filing group, both sides of canal enlargement showed sharply difference(p<0.01). 4. The percentage of canal enlargement on convex side was greater than that of on concave side in the third of cervix of the engine-driven nickel-titanium file type and the ultrasonically filling. The percentage of canal enlargement of convex and concave side in the third of middle of the engine-driven nickel-titanium Gates-Glidden drill type show a similar canal enlargement between convex side and concave side. As above result, the engine-driven nickel-titanium file type was greater in canal enlargement than the other instruments. The engine-driven nickel-titanium Gates-Glidden dirll type was efficient endodontic instrument for curved canal preparation because it was least change in canal curvature.

• 대한전자공학회논문지
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• 제13권1호
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• pp.11-15
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• 1976

게이트 전류가 흐르지 않는 MOSFET를 사용한 단안정 멀티바치브레이터는 도전시에도 게이트 전압이 일정하게 유지되지 않기 때문에 이 전압을 기준으로 한 회로해석이나 설계는 매우 어려워서, 비교적 간단히 해결할 수있는 도식방법을 소개하였다. 즉 각FET의 전압이득곡선을 구하고 이 유선의 기본적인 성질과 국로 설계에 이용하는 방법들에 대해서 논하였다. In a MOSFET multivibrator, the gate do not hold into a constant clamp voltage during a conduction period. The analysis of the operation and the 43sign of a MOSFET multivibrator circuit are much more discult than that using a bipolar transistor and a electron tube because of above reason. And therefore, in the designing procedures of the MOSFET monostable multivibrator of this paper, a graphical method is adopted in order to analyze and design easily. The voltage gain curves of the both FETs are drawn using a parameter the voltage Vc across the coupling condenser, and the curves are utilized to investigate the voltages of the drains and the gates and determine the gate bias voltage. The diagram gives also important informations for the design of the multivibrator.

• 전기전자학회논문지
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• 제19권3호
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• pp.288-294
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• 2015

고속동작을 위한 반도체 메모리 제품에서 데이터의 신뢰도를 개선하기 위해 CRC(Cyclic Redundancy Check) 기능이 내장되었으며, 데이터전송 속도 개선을 위해 DBI(Data Bus Inversion) 기능이 내장되었다. DDR4, GDDR4 등의 제품에 추가된 기존의 ATM-8 HEC 코드 방식은 부가회로 면적이 크고(~XOR 700 gates) CRC 처리 시간이 길어서(XOR 6단), 저전력 메모리 제품의 데이터 읽기, 쓰기시 내부 동작 마진(margin)에 적지 않은 부담을 초래한다. 본 논문에서는 저비용, 고속 반도체 메모리에 적합한 CRC방식을 제안하였으며 92%의 부가회로가 개선되었다. 제안한 CRC방식의 저비용 구현을 위해 DBI 기능을 이용하여 데이터 비트 오류 검출율을 보완하였으며, 오류 검출율을 분석하여 기존의 CRC방식과 비교하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.687-690
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• 1998

The full Viterbi detector for EPRML read channel system needs large area due to complex computation. There are several conventional methods to reduce the complexity such as GVA(Generalized Viterbi Algorithm) and BMS(Branch Metric Shift). This paper proposes another method, FVD(Folding Viterbi Detector), that has state transition diagram folded with inverted states. Compared with GVA detector, FVD requires only 61% gates and has lower power consumption and better BER performance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.821-824
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• 1999

In distributed arithmetic-based architecture for an inner product between two length-N vectors, the size of the ROM increases exponentially with N. Moreover, the ROMs are generally the bottleneck of speed, especially when their sire is large. In this paper, a ROM size reduction technique for DA (Distributed Arithmetic) is proposed. The proposed method is based on modified OBC (Offset Binary Coding) and control circuit reduction technique. By simulations, it is shown that the use of the proposed technique can result in reduction in the number of gates up to 50%.

• 전자공학회논문지B
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• 제30B권5호
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• pp.10-17
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• 1993

This paper suggests a new addition algorithm. A circuit to implement the algorithm and the result of its performance evaluation are presented. The basic idea of the algorithm is that to obtain the sum of two operands, two operands bits are exclusive-ORed and then the result is inverted by the carry from the previous stage. An unique carry prediction method minimizes carry propagation. The proposed circuit has a very simple and regular structure compared with CLA (carry lookahead adder). It also requires less gates for the implementation about 50% and operates faster.

• 스마트미디어저널
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• 제2권4호
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• pp.20-26
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• 2013

This paper presents an approach to Mongolian car plate recognition using artificial neural network. Our proposed method consists of two steps: detection and recognition. In detection step, we implement Flood fill algorithm. In recognition step we proceed to segment the plate for each Cyrillic character, and use an Artificial Neural Network (ANN) machine - learning algorithm to recognize the character. We have learned the theory of ANN and implemented it without using any library. A total of 150 vehicles images obtained from community entrance gates have been tested. The recognition algorithm shows an accuracy rate of 89.75%.

• 대한전기학회논문지
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• 제32권11호
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• pp.404-416
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• 1983

This paper is concerned with the design automation of the sequential machines. The operations of sequential machine can be diveded into two types such as synchronous and asynchronous sequential machine and their realization is treated in separate mode. But, in order to integrate logic circuits in high volume, mixed mode sequential machine uses common circuitry that consists of gates and flip-flops. Proposed sequential machine can be designed by several method, which are hard-wired implementation, firmware realization by PLA and ROM. And then onr example shows the differnces among three design mothods. Finally, computer algorithm(called MINIPLA) is discussed for various application of mixed-mode sequential machine.

• 대한전기학회논문지
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• 제33권2호
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• pp.47-55
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• 1984

This paper is concerned with a computer-aided state assignment, that is, coding race-free internal states of asynchronous sequential circuits, and a method for minimizing the combinational network of asynchronous sequential circuits. The FORTRAN version of the peoposed algorithm results in race-free state assignments and reduction of the number of connections and gates with near minimal hardware cost. Some examples are designed by the proposed computer program to illustrate the algorithm in this paper. Finally, results are compared with those of the other methods.