Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Reduced Complexity Folding EPR4 Viterbi Detector

간단한 구조의 폴딩 EPR4 비터비 검출기

  • 이천수 (고려대학교 대학원 전자공학과 ASIC 연구실) ;
  • 기훈재김수원 (고려대학교 대학원 전자공학과 ASIC 연구실)
  • Published : 1998.10.01
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Abstract

The full Viterbi detector for EPRML read channel system needs large area due to complex computation. There are several conventional methods to reduce the complexity such as GVA(Generalized Viterbi Algorithm) and BMS(Branch Metric Shift). This paper proposes another method, FVD(Folding Viterbi Detector), that has state transition diagram folded with inverted states. Compared with GVA detector, FVD requires only 61% gates and has lower power consumption and better BER performance.

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