• Design & Manufacturing
• /
• v.11 no.3
• /
• pp.29-34
• /
• 2017

Increased demand for parts with micro-pattern structure made of metals, ceramics, and composites in various fields such as medical ultrasonic sensors, CT collimators, and ultra-small actuator parts. Micro powder injection molding (PIM) is a technology for manufacturing micro size, high volume, complex, precision, net-shape components from either metal or ceramic powder. In the present study, a standard mold with a variable insert core capable of producing various micro patterns was investigated. An injection molding test was performed on a standard mold using a line type micro-pattern core having an aspect ratio of 2, a slenderness ratio of 70, a pattern size of $200{\mu}m$, and a pattern spacing of $150{\mu}m$. During the filling process, the deformation of the mold with large aspect ratio and slenderness ratio was analyzed by the experiment and the numerical simulation according to the position of the gate. We proposed a mold structure that minimizes mold deformation by gate modification and enables uniform pattern filling behavior.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.1
• /
• pp.83-90
• /
• 1986

A micro pH-ISFET probe, which can be applied to the in vivo measurements of the hydrogen ion concentration in blood, has been developed, and a measuring system equiped with this probe also developed. The pH-ISFET has been fatricated by employing the techniques of integrated circuit fabrication. Two kinds of micro electrode formed around the sensing gate during the wafer process, and the other is a capillary type of Ag/AfCl/sat. KCI reduced in size. This capillary electrode has shown its good performance characteristics so far in the application with ISFET as well as a commercial one. In order to form a micro pH-ISFET probe, this pH-ISFET and well as a commercial one. In order to form a micro pH-ISFET probe, this pH-ISFET and the capillary electrode were built together into a needle tip having 1 mm inner diameter. The chip size of a twin pH-ISFET is 0.8 mmx1.4 mm, the material of the sensing gate membrane is Si3N4, and the sensitivity of the developed probe is about 52mV/pH.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.84-87
• /
• 2000

In this paper, a high gain-broad bandwidth MMIC distributed amplifier was designed using cascaded single section distributed amplifier configuration. The PHEMT for this studies was fabricated at our lab The PHEMT has a 0.2 $\mu\textrm{m}$ gate length. a 80 $\mu\textrm{m}$ unit gate width and 4 gate fingers. A designed MMIC amplifier have higher S$\sub$21/ gain than the common distributed amplifier using the same number of active devices. From the simulated result, we obtained that the S$\sub$21/ gain of DC ∼ 20 GHz bandwidth was 15.6 dB and flatness was ${\pm}$0.9 dB, and input and output reflection coefficient were lower than -8 dB. The simulated gain shows an improvement 7.3 dB compared with those of conventional distributed amplifier. And the chip size is 2.0 ${\times}$ 1.2 $\textrm{mm}^2$.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.1
• /
• pp.40-49
• /
• 2001

We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}Ｖ_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.9 no.4
• /
• pp.192-197
• /
• 2009

This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in $0.18\;{\mu}m$ CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is $1.0\;mm{\times}0.9\;mm$ including pads.

• Transactions of Materials Processing
• /
• v.18 no.2
• /
• pp.160-165
• /
• 2009

A Study on Effects of the Runner and the Gate of double shot injection molded Parts using CAE Double shot injection molding can inject two different materials or two different colors in the same mold in a injection molding process. Double shot injection molded parts can be characterized that the base part maintains strength and specified part can inject soft-material. It can reduce the production cost by single automatic operations. In this paper, we designed double shot injection mold for automobile emote control To inject secondary part, this part is used as an insert after external appearance of product is injected. CAE analysis was progressed gate location and runner size as variables. The analysis result is reflected in mold design process. As a result, it could solve problems which are generated in the conventional mold. Additionally, cost can be downed by reducing runner weight. As well as it could omit painting process because the surface of finished product is improved through new mold.

• ETRI Journal
• /
• v.36 no.1
• /
• pp.89-98
• /
• 2014

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.1
• /
• pp.27-31
• /
• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.33 no.8
• /
• pp.793-798
• /
• 2009

In this paper, the simulation and optimization of SRH (Surface Relief Hologram) masks for printing LCD gate patterns using TIR (Total Internal Reflection) holographic lithography was investigated. A simulation and optimization algorithm based on SDTA (Scalar Diffraction Theory Analysis) method was developed. The accuracy of the algorithm was compared to that of the RCWA (Rigorous Coupled Wave Analysis) method for estimating the Fresnel diffraction pattern of Cr amplitude masks for the given system geometry. In addition, the results from the optimization algorithm were validated experimentally. It was found that one to the most important conditions for the fabrication of SRH masks is to avoid nonlinear shape distortions of the resulting grating. These distortions can be avoided by designing SRH masks with recorded gratings having small aspect ratios of width versus depth. The optimum gap size between the Cr and SRH masks was found using the optimization algorithm. A printed LCD gate pattern with a minimum line width of $1.5{\mu}m$ exposed using the optimized SRH mask was experimentally demonstrated.

• Journal of Power Electronics
• /
• v.16 no.2
• /
• pp.786-797
• /
• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.