• 소성∙가공
• /
• 제12권2호
• /
• pp.134-140
• /
• 2003

Polymers such as polypropylene or polyethylene offer a unique feature of producing an integral hinge, which can flex over a million times without causing a failure. With such advantage manufacturing, time and cost required at the assembly stage can be eliminated by injecting the whole part as one piece. However, due to increased fluidity resistance at hinges during molding, several defects such as short shot or premature hinge failure can occur with the improper selection of gate locations. Therefore, it is necessary to optimize flow balancer in injection molding of part with hinges before actually producing molds. In this paper, resin flow patterns depending on several gate positions were investigated by numerical analyses of a simple strip part with a hinge. As a result, we found that the properly determined gate location leads to better resin flow and shorter hesitation time. Finally, injection molding tryouts using a mold that was designed one of the proposed gate systems were conducted using polypropylene that contained 20% talc. The experiment showed that hinges without defects could be produced by using the designed gate location.

• 한국전기전자재료학회논문지
• /
• 제26권10호
• /
• pp.713-719
• /
• 2013

Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have optimal designed planar and trench gate power MOSFET for high breakdown voltage and low on resistance. When we have designed $6,580{\mu}m{\times}5,680{\mu}m$ of chip size and 20 A current, on resistance of trench gate power MOSFET was low than planar gate power MOSFET. The on state voltage of trench gate power MOSFET was improved from 4.35 V to 3.7 V. At the same time, we have designed unified field limit ring for trench gate power MOFET. It is Junction Termination Edge type. As a result, we have obtained chip shrink effect and low on resistance because conventional field limit ring was convert to unify.

• 예술인문사회 융합 멀티미디어 논문지
• /
• 제7권3호
• /
• pp.301-310
• /
• 2017

양자점 셀룰라 오토마타(QCA: quantum-dot cellular automata)는 나노 크기의 셀을 이용하여 다양한 연산을 수행하며, 매우 빠른 연산속도와 적은 전력손실로 차세대 기술로 떠오르고 있다. 본 논문에서는 QCA 상에서 새로운 유니버셜 게이트(universal gate)를 제안한다. 또한, 유니버셜 게이트를 이용하여 시공간 효율성 측면에서 우수한 XOR 게이트를 제안한다. 유니버셜 게이트는 자기 자신으로 모든 기본 논리 게이트를 만들어 낼 수 있는 게이트이다. 한편, 제안된 유니버셜 게이트는 기본 셀과 회전된 셀을 활용하여 설계한다. 제안된 유니버셜 게이트의 회전된 셀은 3-입력 다수결게이트 구조의 중앙부에 위치한다. 3-입력 다수결 게이트를 이용하여 XOR 게이트를 설계할 때는 5개 이상의 3-입력 다수결 게이트가 사용되지만, 본 논문에서는 3개의 유니버셜 게이트를 사용하여 XOR 게이트를 제안한다. 제안하는 XOR 게이트는 기존의 XOR 게이트보다 사용된 게이트 수가 줄었으며 설계 면적이나 소요 클럭면에서 우수함을 확인할 수 있다.

• 한국전기전자재료학회논문지
• /
• 제25권4호
• /
• pp.253-260
• /
• 2012

IGBT (insulated gate bipolar transistor) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the on state voltage drop should be lowered and the switching time should be shorted. However, there is Trade-off between the breakdown voltage and the on state voltage drop. To achieving good electrical characteristics, field stop IGBT (FS IGBT) is proposed. In this paper, 1,200 V planar gate non punch-through IGBT (planar gate NPT IGBT), planar gate FS IGBT and trench gate FS IGBT is designed and optimized. The simulation results are compared with each three structures. In results, we optain optimal design parameters and confirm excellence of trench gate FS IGBT. Experimental result by using medici, shows 40% improvement of on state voltage drop.

• 한국전기전자재료학회논문지
• /
• 제31권4호
• /
• pp.208-211
• /
• 2018

This paper details the design of a 1,200 V class trench gate field stop IGBT (insulated gate bipolar transistor) with a nano gate structure smaller than 1 um. Decreasing the size is important for lowering the cost and increasing the efficiency of power devices because they are high-voltage switching devices, unlike memory devices. Therefore, in this paper, we used a 2-D device and process simulations to maintain a gate width of less than 1 um, and carried out experiments to determine design and process parameters to optimize the core electrical characteristics, such as breakdown voltage and on-state voltage drop. As a result of these experiments, we obtained a wafer resistivity of $45{\Omega}{\cdot}cm$, a drift layer depth of more than 180 um, an N+ buffer resistivity of 0.08, and an N+ buffer thickness of 0.5 um, which are important for maintaining 1,200 V class IGBTs. Specially, it is more important to optimize the resistivity of the wafer than the depth of the drift layer to maintain a high breakdown voltage for these devices.

• 한국항해항만학회:학술대회논문집
• /
• 한국항해항만학회 2005년도 추계학술대회 논문집
• /
• pp.125-131
• /
• 2005

게이트 운영은 수출 컨테이너를 위한 시작점이면서 수입 컨테이너의 종착점으로 컨테이너의 확인과 통제가 필요한 중요한 시설물이다. 본 연구의 목적은 컨테이너터미널 내부의 차량 통행량을 분산시키면서 차량의 체재시간을 감소시키기 위한 분리게이트 설계방안을 제안하는 것이다. 대량의 컨테이너가 단기간에 하역되기 때문에 많은 차량이 일시에 게이트를 통과해야 한다. 본 연구는 두개의 개별 선석의 통합을 고려한 게이트 운영을 위한 효과적인 설계로서 분리 게인트시스템을 제안한다.

• 한국철도학회:학술대회논문집
• /
• 한국철도학회 2009년도 춘계학술대회 논문집
• /
• pp.1943-1950
• /
• 2009

The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The gate oxide structure gives the main influence on the changes in the electrical characteristics affected by environments such as radiation and temperature, etc.. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide. In this paper, the electrical characteristics are simulated by SPICE simulation, and the parameters are found to design optimized circuits.

• 전기전자학회논문지
• /
• 제25권2호
• /
• pp.381-387
• /
• 2021

과거 주로 게임과 동영상 재생에 있어 리얼함을 극대화하기 위해 사용되었던 HMD(Head Mount Display)의 수요가 증가하고, 그 활용 범위가 교육과 훈련 등으로 확대되면서, 기존 HMD의 성능을 향상시킬 수 있는 방안에 대한 관심이 높아지고 있다. 본 논문에서는 HMD의 각 화소 회로에 제어 신호를 보내는 gate driver의 성능을 향상시키기 위해 CNT를 포함한 트랜지스터를 활용하는 방법에 대해 논하고자 한다. 기존 gate driver의 버퍼부를 구성하는 트랜지스터를 CNT를 포함한 트랜지스터로 교체하는 회로 설계 방법을 제안하고, 그 성능을 회로 시뮬레이션을 통해 기존 트랜지스터로만 구성된 gate driver의 성능과 비교해 보고자 한다. 시뮬레이션 결과, gate driver에 CNT를 포함할 경우 12.5 GHz의 속도로 기존 gate driver 대비 약 0.3V 증가된 출력 전압(1.1V)을 얻을 수 있었으며, 최대 20배의 gate width를 줄일 수 있었다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1999년도 하계학술대회 논문집 D
• /
• pp.1809-1811
• /
• 1999

In recent years, attempts have been made to greatly improve the display quality of active-matrix liquid crystal display devices, and many techniques have been proposed to solve such problems as gate delay, feed-through voltage and image sticking. Gate delay is one of the biggest limiting factors for large-screen-size, high-resolution thin-film transistor liquid crystal display (TFT/LCD) design. Many driving method proposed for TFT/LCD progress. Thus we developed gate driving signal generator. Since Pixel-Design Array Simulation Tool (PDAST) can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the driving signals of gate lines on the pixel operations can be effectively analyzed.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 1996년도 춘계학술대회 논문집
• /
• pp.787-791
• /
• 1996

In injection molding, location of gates have great influence on the quality of plastic parts. Usually, they are located by releated trial and errors of experienced mold designers. In this topic we will present the numerical algorithm for finding the optimal gate locations. Optimization algorithm is devided into two stages. In the first stage, candidated optimal gate locations can be found by geometry of part only; whereas in the next step, more acculate gate locations are selected byiterative computation with optimization part and analysis part. So from the following study, we suggested the modified flow-volume method, which will define the optimal gate locations in injection mold design.