• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.77-79
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• 1992

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05c
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• pp.148-152
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• 2001

One set of MMIC library has been developed using gate recess etching by spin processor. It is superior than that of dipping Method in the uniformity and the reproducibility of gate recess. A DC characteristics of p-HEMT have a uniform characteristics in the whole wafer than that of dipping method. The low noise p-HEMT with the $0.6{\mu}m$ and $200{\mu}m$ of gate length and gate width, respectivily, has a uniform characteristics of Idss 130~145 mA, conductances 190~220mS/nm, and threshold voltage -0.7~-1.1V in the drain voltage of 2V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.11
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• pp.895-900
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• 2000

In this paper, C-V characteristics based on the structure of GaAs MESFET’s has been proposed with wide range of applied voltages and temperatures. Small signal capacitance; gate-source and gate-drain capacitances are represented by analytical expressions which are classified into two different regions; linear and saturation regions with bias voltages. The expression contains two variables; the built-in voltage( $V_{vi}$ )and the depletion width(W). Submicron gate length MESFETs has been selected to prove the validity of the theoretical perdiction and shows good agreement with the experimental data over the wide range of applied voltages.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.135-141
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• 2014

In this paper, the device design guideline to reduce the threshold voltage variation with fin width in junctionless MuGFET has been suggested. It has been observed that the threshold voltage variation was increased with increase of fin width in junctionless MuGFETs. To reduce the threshold voltage variation with fin width in junctionless MuGFETs, 3-dimensional device simulation with different gate dielectric materials, silicon film thickness, and an optimized fin number has been performed. The simulation results showed that the threshold voltage variation can be reduced by the gate dielectric materials with a high dielectric constant such as $La_2O_3$ and the silicon film with ultra-thin thickness even though the fin width is increased. Particularly, the reduction of the threshold voltage variation and the subthreshold slope by reducing the fin width and increasing the fin numbers is known the optimized device design guideline in junctionless MuGFETs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.8-14
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• 2012

The device performances of n-channel MuGFET with different fin numbers and fin widths but the total effective channel width is constant have been characterized. Two kinds of Pi-gate devices with fin number=16, fin width=55nm, and fin number=14, fin width=80nm have been used in characterization. The threshold voltage, effective electron mobility, threshold voltage roll-off, inverse subthreshold slope, PBTI, hot carrier degradation, and drain breakdown voltage have been characterized. From the measured results, the short channel effects have been reduced for narrow fin width and large fin numbers. PBTI degradation was more significant in devices with large fin number and narrow fin width but hot carrier degradation was similar for both devices. The drain breakdown voltage was higher for devices with narrow fin width and large fin numbers. With considering the short channel effects and device degradation, the devices with narrow fin width and large fin numbers are desirable in the device layout of MuGFETs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.23-30
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• 2006

This paper describes the short-channel effect(SCE), corner effect of nano-scale MuGFETs(Multiple-Gate FETs) by three-dimensional simulation. We can extract the equivalent gate number of MuGFETs(Double-gate=2, Tri-gate=3, Pi-gate=3.14, Omega-gate=3.4, GAA=4) by threshold voltage model. Using the extracted gate number(n) we can calculate the natural length for each gate devices. We established a scaling theory for MuGFETs, which gives a optimization to avoid short channel effects for the device structure(silicon thickness, gate oxide thickness). It is observed that the comer effects decrease with the reduction of doping concentration and gate oxide thickness when the radius of curvature is larger than 17 % of the channel width.

• Journal of Industrial Technology
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• v.29 no.B
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• pp.47-56
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• 2009

University is very big scale among urban facilities as for single facilities and there is characteristic that accompany various university support functions in contiguity area. Width that have diverse spatial configuration generally our country university campus around was formed, this does function that connect university and ambit. Specially, formation enables change of spatial configuration that existent width system has if is new around university campus. Also, can form more animate and lively width spatial configuration by forming more various and complex width spatial configuration in width had formed in existing. It is that search special quality of university surrounding width spatial configuration analyzing existing width spatial configuration of Kangwon National University back gate by formation if this study is new in city and forecasts the change, and used space syntax by spatial configuration analysis method.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.302-305
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• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.3
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• pp.34-39
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• 2004

This research investigated the influence on the 4 cell of DC discharge on the side of the discharge characteristic. This DC discharge cells are that composes AND gate of AND gate PDP newly proposed. As for the discharge starting voltage of this discharge cell of 4 pieces, it has been understood that there is deeply a relation up to the space charge generated from the discharge of adjoining discharge cell through the experiment. The discharge voltages which had become each discharge cell optimizations from the experiment result were decided. Moreover, the width of the margin of two AND input voltages is wide and the AND function occurs clearly. However, it has been qualitatively understood that it is difficult enough to obtain the operation margin of the DC priming discharge used to address discharge of PDP.

• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.42-44
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• 2007

The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr) $1500{\AA}$ under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these, thin films is formed with a-SiN:H ($2000{\mu}m$), a-Si:H($2000{\mu}m$) and $n^+a-Si:H$ ($500{\mu}m$). We have deposited $n^+a-Si:H$, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the $n^+a-Si:H$ layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain show drain current of $8{\mu}A$ at 20 gate voltages, $I_{on}/I_{off}$ ratio of ${\sim}10^8$ and $V_{th}$ of 4 volts.