References
- International Technology Roadmap for semiconductor, http://public.itrs.net
- J.P Colinge et al.,'Thin Film SOI Technology: The solution to Many submicron CMOS Problems,' Tech. of Digest IEDM., pp. 817-820, 1989 https://doi.org/10.1109/IEDM.1989.74178
- R.Chau et al.,'A 50nm depleted CMOS transistor(DST)', Technical Digest of IEDM., pp. 621-624, 2001
- T. Sekigawa, Y. Hayashi, 'Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate' Solid state Electron., vol 27, pp.827-828, 1984 https://doi.org/10.1016/0038-1101(84)90036-4
- D. Hisamoto et al., 'FinFETa self-aligned double-gate MOSFET scalable to 20nm' IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec 2000 https://doi.org/10.1109/16.887014
- R. Chau et al., 'Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate,' in Intl. Conf. on Solid State Dev ices and Materials, pp, 68-69, 2002
- J,-T. Park, J,-P. Colinge, and C. H. Diaz, 'Pi-Gate SOI MOSFET,' IEEE Electron Device Letters, vol. 22, no. 8, pp. 405-406, Aug 2001 https://doi.org/10.1109/55.936358
- F-L. Yang, H-Y Chen, F-C. Cheng, C-C Huang, C-Y Chang, H-K Chiu, '25 nm CMOS Omega FETs', Technical Digest of IEDM, pp. 255-258, 2000 https://doi.org/10.1109/IEDM.2002.1175826
- J.P. Colinge, M.H. Gao, A Romano-Rodriguez, H. Maes, and C. Claeys, 'Silicon-on-insulator gate-all-around device', Technical Digest of the IEDM, pp. 595-598, 1990 https://doi.org/10.1109/IEDM.1990.237128
- http://www.silvaco.com
- Christoper P. Auth and James D. Plummer, 'A Simple Model for Threshold Voltage of Surrounding-Gate MOSFETs,' IEEE Trans. Electron Devices, vol. 45, no. 11, pp.2381 -2383, Nov 1998 https://doi.org/10.1109/16.726665
- Kunihiro Suzuki, Tetsu Tanaka, Yoshiharu Tosaka, Hiroshi Hone, and Yoshihiro Arimoto, 'Scaling Theory for Double-Gate SOI MOSFET's,' IEEE Trans. Electron Devices, vol. 40, no. 12, pp.23262329, Dec 1993 https://doi.org/10.1109/16.249482
- Christoper P. Auth and James D. Plummer, 'Scaling Theory for Cylindrical Fully- Depleted, Surrounding-Gate MOSFETs,' IEEE Electron Device Letters, vol. 22, pp.487-489 https://doi.org/10.1109/55.553049
- W.Xiong, J.W. Park, and J.P. Colinge., 'Comer effect in multiple-gate SOI MOSFETs' ,Proceedings of the IEEE International SOI Conference, 2003, pp, 111-113 https://doi.org/10.1109/SOI.2003.1242919
- H-S, Wong. et al., 'Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFETs', Solid state Electron., vol 30, no 9, pp. 953-968, 1987 https://doi.org/10.1016/0038-1101(87)90132-8
- J.P. Colinge, J.W. Park, and W. Xing, 'Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs', IEEE Electron Device Letters, vol. 24, pp. 515-517, 2003 https://doi.org/10.1109/LED.2003.815153