• Title, Summary, Keyword: SOI

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Reduction of short channel Effects in Ground Plane SOI MOSFET′s (Growld Plane SOI MOSFET의 단채널 현상 개선)

  • ;;;;Jean-Pierre Colinge
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.4
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    • pp.9-14
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    • 2004
  • This paper reports the measurement and analysis of the short channel effects and the punchthrough voltage of SOI-MOSFET with a self-aligned ground plane electrode in the silicon mechanical substrate underneath the buried oxide. When the channel length is reduced below 0.2${\mu}{\textrm}{m}$ it is observed that the threshold voltage roll-off and the subthreshold swing with channel length are reduced and DIBL is improved more significantly in GP-SOI devices than FD-SOI devices. It is also observed from the dependence of threshold voltage with substrate biases that the body factor is a higher in GP-SOI devices than FD-SOI devices. From the measurement results of punchthrough voltage, GP-SOI devices show the higher punchthrough voltages than FD-SOI devices

Characteristic Study for Defect of Top Si and Buried Oxide Layer on the Bonded SOI Wafer (Bonded SOI wafer의 top Si과 buried oxide layer의 결함에 대한 연구)

  • Kim Suk-Goo;Paik Un-gyu;Park Jea-Gun
    • Korean Journal of Materials Research
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    • v.14 no.6
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    • pp.413-419
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    • 2004
  • Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

Electrical Characterization of Nano SOI Wafer by Pseudo MOSFET (Pseudo MOSFET을 이용한 Nano SOI 웨이퍼의 전기적 특성분석)

  • Bae, Young-Ho;Kim, Byoung-Gil;Kwon, Kyung-Wook
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.12
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    • pp.1075-1079
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    • 2005
  • The Pseudo MOSFET measurements technique has been used for the electrical characterization of the nano SOI wafer. Silicon islands for the Pseudo MOSFET measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo MOSFET were not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device were dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100 nm SOI was obtained by thinning the silicon film of standard thick SOI wafer. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching Process dependency is greater in the thinner SOI wafer.

A Study on Fabrication of SOI Wafer by Hydrogen Plasma and SOI Power Semiconductor Devices (수소 플라즈마를 이용한 SOI 기판 제작 및 SOI 전력용 반도체 소자 제작에 관한 연구)

  • Sung, Man-Young
    • Proceedings of the KIEE Conference
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    • pp.250-255
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    • 2000
  • 본 "수소 플라즈마를 이용한 SOI 기판 제작 및 SOI 전력용 반도체 소자 제작에 관한 연구"를 통해 수소플라즈마 전처리 공정에 의한 실리콘 기판 표면의 활성화를 통해 실리콘 직접 접합 공정을 수행하여 접합된 기판쌍을 제작할 수 있었으며, 접합된 기판쌍에 대한 CMP(Chemical Mechanical Polishing) 공정을 통해 SOI(Silicon on Insulator) 기판을 제작할 수 있었다. 아울러, 소자의 동작 시뮬레이션을 통해 기존 SOI LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자에 비해 동작 특성이 향상된 이중 채널 SOI LIGBT 소자의 설계 파라미터를 도출하였으며, 공정 시뮬레이션을 통해 소자 제작 공정 조건을 확립하였고, 마스크 설계 및 소자 제작을 통해 본 연구 수행으로 개발된 SOI 기판의 전력용 반도체 소자 제작에 대한 가능성을 확인할 수 있었다.

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Carrier Mobility Enhancement in Strained-Si-on-Insulator (sSOI) n-/p-MOSFETs (Strained-SOI(sSOI) n-/p-MOSFET에서 캐리어 이동도 증가)

  • Kim, Kwan-Su;Jung, Myung-Ho;Choi, Chel-Jong;Cho, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • pp.73-74
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    • 2007
  • We fabricated strained-SOI(sSOI) n-/p-MOSFETs and investigated the electron/hole mobility characteristics. The subthreshold characteristics of sSOI MOSFETs were similar to those of conventional SOI MOSFET. However, The electron mobility of sSOI nMOSFETs was larger than that of the conventional SOI nMOSFETs. These mobility enhancement effects are attributed to the subband modulation of silicon conduction band.

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Characterization of the High Luminance Top Emission Organic Light-emitting Devices (TEOLEDs) Using Dual Cathode Layer (이중 음극층을 이용한 고휘도 전면발광(Top emission) 유기EL소자의 특성평가)

  • Kang, Yoon-Ho;Lee, Su-Hwan;Shin, Dong-Won;Kim, Sung-Jun;Kim, Dal-Ho;Lee, Gon-Sub;Park, Jea-Gun
    • Journal of the Semiconductor & Display Technology
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    • v.5 no.3
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    • pp.23-27
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    • 2006
  • Recently, Top emission organic light-emitting diode (TEOLED) has been attracted by their potential application for the development of flat panel display (FPD). We have fabricated the high luminance top emission organic-emitting diode (TEOLED) using dual cathode layer and three top emitting structure. These devices were characterized by electroluminescence (EL) and current density-voltage (J-V) measurements. After compared it with Au anode structure, luminance of the device using dual anode was better than using without Al device. Consequently, Al layers are very good candidates for a promising electron-injecting buffer layer for top emission light-emitting diode (TEOLED).

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Silicon-Wafer Direct Bonding for Single-Crystal Silicon-on-Insulator Transducers and Circuits (단결정 SOI트랜스듀서 및 회로를 위한 Si직접접합)

  • Chung, Gwiy-Sang;Nakamura, Tetsuro
    • Journal of Sensor Science and Technology
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    • v.1 no.2
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    • pp.131-145
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    • 1992
  • This paper has been described a process technology for the fabrication of Si-on-insulator(SOI) transducers and circuits. The technology utilizes Si-wafer direct bonding(SDB) and mechanical-chemical(M-C) local polishing to create a SOI structure with a high-qualify, uniformly thin layer of single-crystal Si. The electrical and piezoresistive properties of the resultant thin SOI films have been investigated by SOI MOSFET's and cantilever beams, and confirmed comparable to those of bulk Si. Two kinds of pressure transducers using a SOI structure have been proposed. The shifts in sensitivity and offset voltage of the implemented pressure transducers using interfacial $SiO_{2}$ films as the dielectrical isolation layer of piezoresistors were less than -0.2% and +0.15%, respectively, in the temperature range from $-20^{\circ}C$ to $+350^{\circ}C$. In the case of pressure transducers using interfacial $SiO_{2}$ films as an etch-stop layer during the fabrication of thin Si membranes, the pressure sensitivity variation can be controlled to within a standard deviation of ${\pm}2.3%$ from wafer to wafer. From these results, the developed SDB process and the resultant SOI films will offer significant advantages in the fabrication of integrated microtransducers and circuits.

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