• Journal of the Korean Institute of Landscape Architecture
• /
• v.33 no.4 s.111
• /
• pp.33-44
• /
• 2005

In order to reveal the geographical landscape's features of the East Sea-gateway(東海口), which has existed only in the era of Shilla as unique east path, we have carried out analysis of the old maps(邑誌圖) and satellite imagery, and geographical features analysis in the application of digital maps, and the result is as follows. 1. Analysis of materials from the Chosun dynasty describes landscapes called sea gates(海口) (note that this should not be capitalized); a place where the river meets the sea and the sea comes far into the land. Sea gate landscapes may have an island, but this is not a prerequisite. 2. According to the satellite imagery, the capital city of Shilla Dynasty had five passages. four or them are broad corridors, but one of them is narrow. The east side of the capital city is blocked by mountains and there was an important path which leads into the East Sea. 3. According to the cross section of the mountains, there is the only rule East-path. There was no alternative way. There was only one way-out to the east side from the capital city. This is the unique path which reaches a length of 28km. Judging from this, it seems that this path was called the East Sea-gateway. 4. The landscape of the East Sea-gateway was shaped like the letter 'V' and reached to the landscape of the sea gate. However, the route was blocked - part by the mountains, and also the part in the crisis of loss of path-landscape which has lost its own character of closure as several valleys are merged together.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.10 no.2
• /
• pp.97-102
• /
• 2010

In this paper, an area-efficient FFT processor is proposed for IEEE 802.16e mobile WiMax systems. The proposed scalable FFT processor can support the variable length of 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 16% and 27%, respectively, compared with those of the 4-channel radix-2 MDC (R2MDC) FFT processor.

• Journal of IKEEE
• /
• v.22 no.2
• /
• pp.344-349
• /
• 2018

Low temperature variation of electrical characteristics for AlGaN/GaN/HEMT was studied. To investigate the effect of temperatures, transistor was cool down to $-178^{\circ}C$ and electrical characteristics were measured. The drain current density of an AlGaN/GaN HEMT with a gate length of $2{\mu}m$ was increased from 264 mA/mm to 388 mA/mm and the maximum transconductance was increased from 105 mS/mm to 134 mS/mm by decreasing the temperature to $-108^{\circ}C$. Also, the threshold voltage was shifted -0.39 V with the temperature. The reason for the variations was seemed to the reduced channel resistance corresponding to the temperature. However, most of the variation of the electrical characteristics takes places above $-108^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.3
• /
• pp.34-38
• /
• 2000

This paper describes design, fabrication, and performance of an ultra-high-speed and low-noise MMIC (Monolithic Microwave Integrated Circuit) preamplifier for a 10 Gb/s optical receiver. The transimpedance type 3-stage MMIC preamplifier for ultra-high-speed and low-noise was designed using an AlGaAs/InGaAs/GaAs P-HEMTs(Pseudomorphic High Electron Mobility Transistors) with 0.15${\mu}{\textrm}{m}$ length T-shaped gate. To obtain broadband characteristics, we used the inductor peaking technique, and the gate width was optimized for low noise performance. Measurements reveal that the fabricated preamplifier has the high transimpedance gain of 60 ㏈Ω and 9.15 ㎓ bandwidth with the noise figure of less than 3.9 ㏈.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.6
• /
• pp.1-7
• /
• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.12 no.2
• /
• pp.22-29
• /
• 2013

The platform safety door is difficult to install in platform because the doors of railway vehicles and existing Passenger Safety doors should be alined. To be able to solve this problem, we propose the use of Rope Type Platform Safe Door (RPSD) which is a vertically retractable platform that is designed to close from top to bottom. This platform has installed safety gate pillars at intervals of 20-40 m which accommodates different types of train regardless of train length, gate opening and location. In this paper, we reviewed the application of existing PSD and RPSD in various train stops in Seoul Gyeongbu Line platform. The results of the review showed that the existing PSD may cause problem in construction, safety and cost efficiency. The use of RPSD however shows that minimal problems will be encountered.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.11
• /
• pp.1-10
• /
• 1998

The advent of deep submicron technologies in the age of portable electronic systems creates a moving target for CAB algorithms, which now need to reduce power as well as delay and area in the existing design methodology. This paper presents a resynthesis algorithm for logic decomposition on mapped circuits. The existing algorithm uses a Huffman encoding, but does not consider glitches and effects on logic depth. The proposed algorithm is to generalize the Huffman encoding algorithm to minimize the switching activity of non-critical subcircuits and to preserve a given logic depth. We show how to obtain a transition-optimum binary tree decomposition for AND tree with zero gate delay. The algorithm is tested using SIS (logic synthesizer) and Level-Map (LUT-based FPGA lower power technology mapper) and shows 58%, 8% reductions on power consumptions, respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.2
• /
• pp.301-306
• /
• 2015

An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a $0.25{\mu}m$ GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the $3{\times}3-mm^2$ QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses ($S_{11}$ and $S_{22}$) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is $1.1{\times}0.9mm^2$. To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.7
• /
• pp.1463-1469
• /
• 2012

This paper has presented the influence of scaling theory on short channel effects of double gate(DG) MOSFET in subthreshold region. In the case of conventional MOSFET, to preserve constantly output characteristics,current and switching frequency have been analyzed based on scaling theory. To analyze the results of application of scaling theory for short channel effects of DGMOSFET, the changes of threshold voltage, drain induced barrier height and subthreshold swing have been observed according to scaling factor. The analytical potential distribution of Poisson equation already verified has been used. As a result, it has been observed that threshold voltage among short channel effects is grealty changed according to scaling factor. The best scaling theory for DGMOSFET has been explained as using modified scaling theory, applying weighting factor reflected the influence of two gates when scaling theory has been applied for channel length.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.08a
• /
• pp.254-254
• /
• 2011

The memories with nano-particles are very attractive because they are promising candidates for low operating voltage, long retention time and fast program/erase speed. In recent, various nano-floating gate memories with metal-oxide nanocrystals embedded in organic and inorganic layers have been reported. Because of the carrier generation in semiconductor, induced photon pulse enhanced the program/erase speed of memory device. We studied photo-induced electrical properties of these metal-oxide nanocrystal memory devices. At first, 2~10-nm-thick Sn and In metals were deposited by using thermal evaporation onto Si wafer including a channel with $n^+$ poly-Si source/drain in which the length and width are 10 ${\mu}m$ each. Then, a poly-amic-acid (PAA) was spin coated on the deposited Sn film. The PAA precursor used in this study was prepared by dissolving biphenyl-tetracarboxylic dianhydride-phenylene diamine (BPDA-PDA) commercial polyamic acid in N-methyl-2-pyrrolidon (NMP). Then the samples were cured at 400$^{\circ}C$ for 1 hour in N atmosphere after drying at 135$^{\circ}C$ for 30 min through rapid thermal annealing. The deposition of aluminum layer with thickness of 200 nm was followed by using a thermal evaporator, and then the gate electrode was defined by photolithography and etching. The electrical properties were measured at room temperature using an HP4156a precision semiconductor parameter analyzer and an Agilent 81101A pulse generator. Also, the optical pulse for the study on photo-induced electrical properties was applied by Xeon lamp light source and a monochromator system.