• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.61-61
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• 2009

P-type SGS-TFTs with 10 ${\mu}m$ channel length and two channel widths; $W_1=5{\mu}m$ and $W_2=10{\mu}m$ which has gate insulator made of 20nm $SiO_2$ and 80nm SiNx was fabricated and the electrical properties of them were measured. The field-effect mobility was increased from 95.84 to 104.19 $cm^2/V-s$ and threshold voltage also increased from -0.802 V to -0.954 V, when channel width is increased from5 ${\mu}m$ to 10 ${\mu}m$. Subthreshold swing decreased from 0.418 to 0.343 V/dec and $I_{on/off}$ ratio increased from $4.77{\times}10^7$ to $7.30{\times}10^7$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.62-62
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• 2009

Electrical properties of SGS-TFT with 5/5 ${\mu}m$ channel width and length which gate insulator is made of 20nm $SiO_2$ and 80nm $SiN_x$ was fabricated and measured at various temperatures. The field-effect mobility was decreased from 86.25 to 80.42 $cm^2/Vs$ and threshold voltage also decreased from -1.5792 to -1.0492 V, when temperature is increased from room temperature to $100^{\circ}C$. Subthreshold swing, also, increased from 0.3212 to 0.4818 V/dec and $I_{on/off}$ ratio decreased from $5.05{\times}10^7$ to $6.93{\times}10^5$.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.579-582
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• 2005

In this study, the electrical characteristic of asymmetric high voltage MOSFET (AHVMOSFET) for display IC was investigated. Measurement data are taken over range of temperature (300K-400K) and various extended drain length, and gate oxide thickness ($175{\AA}$, $350{\AA}$). In high temperature condition, drain current decreased over 30% and max transconductance deceased over 40%, and specific on-resistance increased over 30% in comparison with room temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.139-142
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• 2008

An X-band MMIC power amplifier for radar application is developed using $0.25-{\mu}m$ gate length GaAs pHEMT technology. A bus-bar power combiner at output stage is used to minimize the combiner size and to simplify bias network. The fabricated power amplifier shows 38.75 dBm (7.5 Watt) Psat at 10 GHz. The chip size is $3.5\;mm{\times}3.9\;mm$.

• 전자공학회논문지B
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• 제33B권4호
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• pp.63-71
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• 1996

In this paper, a variable length block code for real time compression and decompression of hanguel and chinese character bit map font is proposed. The proposed code shows a good compression ratio in complete form of hangeul myoungjo and godik style and chinese batang and doddum style bit map font. Besides, a compression and decompression ASIC is designed and simulated on CAD. The 0.8 micron CMOS sea of gate is used to implement the ASIC in amount of 5,200 gates, and it runs at simple hardware and compress and decompress at 33M bit/sec at maximum, which is ideal for real time applications.

• 소성∙가공
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• 제20권1호
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• pp.73-78
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• 2011

The flashing reduces the part quality and the productivity of the molding process. We developed a contact pressure sensor to detect the flashing immediately. The performance of the sensor was analyzed in a simple 2D simulation. The sensor was applied to an automotive bumper mold with cavity pressure sensors. It showed sensitive output signal for the mold response by the cavity pressure change. It was confirmed that the flashing at the gate area occurred in the filling stage by the pressure increase due to growth of the melt flow length. The sensor output was correlated with the cavity pressure sensor output.

• 한국안전학회지
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• 제31권4호
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• pp.143-149
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• 2016

In this study, a series of numerical simulation of dam break flow was conducted using EFDC model, and input conditions including cell size, time step, and turbulent eddy viscosity were considered to analyze parameter sensitivity. In case of coarse mesh layout, the propagated length of the shock wave front was ${\Delta}_x$ longer than that of other mesh layouts, and the velocity results showed jagged edge, which can be cured by applying fine grid mesh. Turbulent eddy viscosity influenced magnitude of the maximum velocity passing through gate up to 20% and the cell Peclet number less than 2.0 ensured no numerical oscillations.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 추계학술대회 논문집
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• pp.232-235
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• 1995

To improve the DIBL characteristics of deep sub micron BC PMOSFETs, the methods of DCI(Deep Channel Implantation) and Hale Implantation have been reported. In this study, using the process simulator TSUPREM4, we simulated the 0.25$\mu\textrm{m}$ and 0.45$\mu\textrm{m}$ gate length BC PMOSFETs applying the both methods to improve the DIBL characteristics, and their electric characteristics were compared to find the mothod suitable far deep sub-half micron BC PMOSFETs, using the device simulator MEDICI. So we found out that the method of Halo Implantation could be applied to deep sub-half micron BC PMOSFETs for 255 Mbit DRAM.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.384-385
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• 2006

We studied about conductive pastes of the source-drain contacts for OTFTs(organic thin-film transistors) fabricated by direct printing(screen printing) method. We used Ag and conductive carbon black powder as the conductive fillers of pastes. The conductive pastes were manufactured by various dispersing agents and dispersing conditions and source-drain contacts with $100{\mu}m$ of channel length were fabricated. We could obtain the OTFTs which exhibited different field-effect behaviors over a range of source-dram and gate voltages depending on a kind of conductive fillers used conductive pastes.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.53-58
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• 2012

A new on-wafer de-embedding method using thru, short and open patterns sequentially is proposed to eliminate the errors of conventional methods. This "thru-short-open" method is based on the removal of the coupling admittance between input and output interconnect dangling legs. The increase of the de-embedding effect of the lossy coupling capacitance on the cutoff frequency in MOSFETs is observed as the gate length is scaled down to 45 nm. This method will be very useful for accurate RF measurements of nano-scale MOSFETs.