• ETRI Journal
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• 제45권1호
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• pp.171-179
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• 2023

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13㎛-0.16㎛ to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.

• 한국전기전자재료학회논문지
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• 제31권3호
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• pp.146-151
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• 2018

In this study, we compared the threshold-voltage extraction methods of accumulation-type JLDG (junctionless double-gate) MOSFETs (metal-oxide semiconductor field-effect transistors). Threshold voltage is the most basic element of transistor design; therefore, accurate threshold-voltage extraction is the most important factor in integrated-circuit design. For this purpose, analytical potential distributions were obtained and diffusion-drift current equations for these potential distributions were used. There are the ${\phi}_{min}$ method, based on the physical concept; the linear extrapolation method; and the second and third derivative method from the $I_d-V_g$ relation. We observed that the threshold-voltages extracted using the maximum value of TD (third derivatives) and the ${\phi}_{min}$ method were the most reasonable in JLDG MOSFETs. In the case of 20 nm channel length or more, similar results were obtained for other methods, except for the linear extrapolation method. However, when the channel length is below 20 nm, only the ${\phi}_{min}$ method and the TD method reflected the short-channel effect.

• 대한전자공학회논문지SD
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• 제42권3호
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• pp.1-8
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• 2005

본 논문에서는 $0.1\;{\mu}m$ 이하의 게이트 길이를 갖는 MHEMT의 DC 및 RF 특성을 상용 시뮬레이터인 ISE-TCAD tool을 이용하여 결과를 고찰하였다. 이후 MHEMT의 게이트 길이와, 소스-드레인 간격 및 채널 두께를 변화시켜 가면서 소자의 수평, 수직 Scaling효과가 소자 특성에 미치는 영향을 비교하였으며, 게이트 길이 $(L_g)$가 $0.1\;{\mu}m$ 이하로 감소함에 따라 $g_{m,max}$가 같이 감소하는 현상에 대해서 논의해 보았다. 또한 이 현상을 가지고 소자의 횡적, 종적 파라미터의 scaling 효과에 대한 모델을 제시 했다.

• Journal of information and communication convergence engineering
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• 제16권1호
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• pp.43-47
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• 2018

The existing modeling of avalanche dominated breakdown in double gate MOSFETs (DGMOSFETs) is not relevant for 10 nm gate lengths, because the avalanche mechanism does not occur when the channel length approaches the carrier scattering length. This paper focuses on the punch through mechanism to analyze the breakdown characteristics in 10 nm DGMOSFETs. The analysis is based on an analytical model for the thermionic-emission and tunneling currents, which is based on two-dimensional distributions of the electric potential, obtained from the Poisson equation, and the Wentzel-Kramers-Brillouin (WKB) approximation for the tunneling probability. The analysis shows that corresponding flat-band-voltage for fixed threshold voltage has a significant impact on the breakdown voltage. To investigate ambiguousness of number of dopants in channel, we compared breakdown voltages of high doping and undoped DGMOSFET and show undoped DGMOSFET is more realistic due to simple flat-band-voltage shift. Given that the flat-band-voltage is a process dependent parameter, the new model can be used to quantify the impact of process-parameter fluctuations on the breakdown voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.511-515
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• 2013

A Monte Carlo (MC) simulation study has been done in order to investigate the effects of line-edge-roughness (LER) induced by either 1P1E (single-patterning and single-etching) or 2P2E (double-patterning and double-etching) on fully-depleted silicon-on-insulator (FDSOI) tri-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Three parameters for characterizing the LER profile [i.e., root-mean square deviation (${\sigma}$), correlation length (${\zeta}$), and fractal dimension (D)] are extracted from the image-processed scanning electron microscopy (SEM) image for each photolithography method. It is experimentally verified that two parameters (i.e., ${\sigma}$ and D) are almost the same in each case, but the correlation length in the 2P2E case is longer than that in the 1P1E case. The 2P2E-LER-induced $V_TH$ variation in FDSOI tri-gate MOSFETs is smaller than the 1P1E-LER-induced $V_TH$ variation. The total random variation in $V_TH$, however, is very dependent on the other major random variation sources, such as random dopant fluctuation (RDF) and work-function variation (WFV).

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2002년도 추계종합학술대회
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• pp.494-497
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• 2002

본 논문에서는 halo doping profile을 갖는 나노구조 LDD MOSFET의 문턱전압에 대한 시뮬레이션 결과를 나타내었다. 소자 크기는 generalized scaling을 사용하여 100nm에서 40nm까지 스케일링하였다. Van Dort Quantum Correction Model(QM)을 사용하여 정전계 스케일링과 정전압 스케일링에 대한 문턱 전압과 각각의 게이트 oxide 두께에 대한 direct tunneling 전류를 조사하였다. 게이트 길이가 감소할 때 정전계 스케일링에서는 문턱전압이 감소하고, 정전압 스케일링에서는 문턱전압이 증가하는 것을 알 수 있었고, 게이트 oxide두께가 감소할 때 direct tunneling 전류는 증가함을 알 수 있었다. 감소하는 채널 길이를 갖는 MOSFET 문턱전압에 대한 roll-off 특성을 최소화하기 위해 generalized scaling에서 $\alpha$값은 1에 가깝게 되는 것을 볼 수 있었다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 추계학술대회
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• pp.611-613
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• 2016

TCAD 시뮬레이션을 이용하여 소스영역으로 오버랩된(overlapped) 게이트를 가진 터널링 전계효과 트랜지스터(Tunnel Field-Effect Transistor; TFET)의 오버랩된 게이트 길이에 따른 터널링 전류 특성을 조사하였다. 터널링은 크게 라인터널링과 포인트 터널링으로 구분되는데, 라인터널링이 포인트터널링보다 subthreshold swing(SS), on-current에서 더 높은 성능을 보인다. 본 논문은 Silicon, Germanium, Si-Ge Hetero TFET구조에서 게이트 길이를 소스영역으로 오버랩될 경우에 포인트 터널링과 라인터널링의 효과를 조사해서 SS와 on-current에 최적합한 구조의 가이드라인을 제시한다.

• 대한전자공학회논문지SD
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• 제45권11호
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• pp.1-7
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• 2008

본 연구에서는 양자 현상을 고려한 나노미터 MuGFET의 C-V 특성을 분석하기 위하여 2차원 Poisson-$Schr{\ddot{o}}dinger$ 방정식을 self-consisnt하게 풀 수 있는 시뮬레이터를 구현하였다. 소자 시뮬레이터를 이용하여 양자 현상으로 인한 소자크기와 게이트 구조에 따른 게이트-채널 커패시턴스 특성을 분석하였다. 소자의 크기가 감소할수록 단위 면적당 게이트-채널 커패시턴스는 증가하였다. 그리고 게이트 구조가 다른 소자에서는 게이트-채널 커패시턴스가 유효게이트 수가 증가할수록 감소하였다. 이런 결과를 실리콘 표면의 전자농도 분포와 인버전 커패시턴스로 설명하였다 또한 인버전 커패시턴스로부터 소자의 크기 및 게이트 구조에 따른 inversion-layer centroid 길이도 계산하였다.

• EDISON SW 활용 경진대회 논문집
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• 제5회(2016년)
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• pp.365-367
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• 2016

나노와이어 FET은 natural length가 작아 단채널 효과가 MOSFET에 비해 줄어든다는 장점이 있어 미래의 소자 구조로 주목 받고 있다. 그런데 나노와이어 FET을 공정할 때 채널 etching에서 채널이 완벽하게 원형 구조를 가지는 것이 어렵다. 본 논문에서는 gate-all-around 실리콘 나노와이어 FET의 aspect ratio에 따른 트랜지스터의 특성 변화를 알아 보았다. 시뮬레이션 결과, aspect ratio가 작을수록 나노와이어 FET에서의 단채널 효과가 줄어드는 경향을 보였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.