• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.175-181
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• 2010

In this paper, we propose a novel hardware architecture for Rate control module for real time full HD video compression. In the proposed architecture, QP is updated by using the rate control algorithm to every the macroblock line(120MB for Full HD, 20MB for CIF image). Since there are many complex arithmetic and floating point arithmetic in rate control algorithm of JM for H.264, it is impossible to process the rate control algorithm using the integer arithmetic CPU core. So we adopted floating point arithmetic unit in our architecture, and implemented the rate control algorithm using the floating unit. With this implemented hardware, the implemented hardware is verified to be operated in real time.

• The KIPS Transactions:PartB
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• v.13B no.4 s.107
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• pp.429-438
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• 2006

Neural Networks(NNs) are applied for solving a wide variety of nonlinear problems in several areas, such as image processing, pattern recognition etc. Although NN can be simulated by using software, many potential NN applications required real-time processing. Thus they need to be implemented as hardware. The hardware implementation of multi-layer perceptrons(MLPs) in several kind of NNs usually uses a fixed-point arithmetic due to a simple logic operation and a shorter processing time compared to the floating-point arithmetic. However, the fixed-point arithmetic-based MLP has a drawback which is not able to apply the MLP software that use floating-point arithmetic. We propose a design method for MLPs which has the floating-point arithmetic-based fully-pipelining architecture. It has a processing speed that is proportional to the number of the hidden nodes. The number of input and output nodes of MLPs are generally constrained by given problems, but the number of hidden nodes can be optimized by user experiences. Thus our design method is using optimized number of hidden nodes in order to improve the processing speed, especially in field of a repeated processing such as image processing, pattern recognition, etc.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.532-542
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• 2009

Dynamic Thermal Management (DTM) technique is generally used for reducing the peak temperature (hotspot) in the microprocessors. Despite the advantages of lower cooling cost and improved stability, the DTM technique inevitably suffers from performance loss. This paper proposes the DualFloating-Point Adders Architecture to minimize the performance loss due to thermal problem when the floating-point applications are executed. During running floating-point applications, only one of two floating-point adders is used selectively in the proposed architecture, leading to reduced peak temperature in the processor. We also propose a new floorplan technique, which creates Space for Heat Transfer Delay in the processor for solving the thermal problem due to heat transfer between adjacent hot units. As a result, the peak temperature drops by $5.3^{\circ}C$ on the average (maximum $10.8^{\circ}C$ for the processor where the DTM is adopted, consequently giving a solution to the thermal problem. Moreover, the processor performance is improved by 41% on the average by reducing the stall time due to the DTM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.593-602
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• 2006

This paper propose to methodology for deciding suitable bit size that minimizes hardware complexity and performance degradation from floating-point design the fixed-point implementation of downlink traffic channel of IEEE 802.16e OFDMA TDD system. One of the major considering issues for implementing fixed-point design is to select Saturation or Quantization properly with the knowledge of signal distribution by pdf or histogram. Also, through trial and error, we should execute exhaustive computer simulation for various bit sizes, hence obtain appropriate bit size while minimizing performance degradation. We carry out computer simulation to decide the optimized bit size of downlink traffic channel under AWGN and ITU-R M.1225 Veh-A channel model.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.2
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• pp.113-117
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• 2007

We have investigated the effects of doping concentration in polysilicon floating gate on the endurance characteristics of the EEPROM cell haying the structure of spacer select transistor. Several samples were prepared with different implantation conditions of phosphorus for the floating gate. Results show the dependence of doping concentration in polysilicon floating gate on performance of EEPROM cell from the floating gate engineering point of view. All of the samples were endured up to half million programming/erasing cycle. However, the best $program-{\Delta}V_{T}$ characteristic was obtained in the cell doped at the dose of $1{\times}10^{15}/cm^{2}$.

• Proceedings of the KSR Conference
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• 2004.10a
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• pp.756-762
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• 2004

Up to now, the only way is Floating Slab Track System, which cuts off vibration by installing spring between concrete slab and ground for the lines of particularly requiring attenuating vibration. The weak point of Floating Slab Track System is large increase of construction cost because normally the structure is getting bigger. In regards to this matter, Floating Rail Track System has been developed, which cuts off vibration by floating the first cause of vibration rail, and the system is in operation. In the thesis, the application of new attenuating vibration track system has been confirmed by studying theoretical background of Floating Rail Track System and evaluating dynamic deflection of track and attenuating of noise and vibration performance through various measurements from laboratory tests and site inspection.

• Journal of Ocean Engineering and Technology
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• v.15 no.1
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• pp.7-11
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• 2001

In this paper, trapezoid sections and prominence sections were examined to improve the performance of floating breakwater in long waves. The linear potential theory is used and the boundary element method with a matching boundary is employed for numerical computation. The effects of the side slope of the trapezoid section and the geometry ratio of the prominence section on the floating breakwater were examined. It was found that trapezoid sections show lower transmission coefficients than the rectangular sections in the long wave range. In prominence sections the size of the sides are more important than the size of the top. Proper choices of the pontoon type geometry may move the local minimum point of the wave transmission coefficient toward the longer wave ranges and improve the performance of the floating breakwater in the long wave range for a given wave period.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1998.06a
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• pp.240-245
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• 1998

Fuzzy information retrieval which uses the concept of fuzzy relation is able to retrieve documents in the way based on not morphology but semantics, dissimilar to traditional information retrieval theories. Fuzzy information retrieval logically consists of three sets : the set of documents, the set of terms and the set of queries. It maintains a fuzzy relational matrix which describes the relationship between documents and terms and creates a thesaurus with fuzzy relational product. It also provides the user with documents which are relevant to his query. However, there are some problems on building a thesaurus with fuzzy relational product such that it has big time complexity and it uses fuzzy values to be processed with flating-point. Actually, fuzzy values have to be expressed and processed with floating-point. However, floating-point operations have complex logics and make the system be slow. If it is possible to exchange fuzzy values with binary values, we could expect sp eding up building the thesaurus. In addition, binary value expressions require just a bit of memory space, but floating -point expression needs couple of bytes. In this study, we suggest a new method of building a thesaurus, which accelerates the operation of the system by pre-applying an ${\alpha}$-cut. The experiments show the improvement of performance and reliability of the system.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1025-1028
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• 1998

Hardware to implement the parallelized Floating-point rounding algorithm is described. For parallelized additions, we propose an addition module which has carry selection logic to generate two results accoring to the input valuse. A multiplication module for parallelized multiplications is also proposed to generate Sum and Carry bits as intermediate results. Since these modules process data in IEEE standard Floatingpoint double precision format, they are designed for 53-bit significands including hidden bits. Multiplication module is designed with a Booth multiplier and an array multiplier.