• Journal of the Optical Society of Korea
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• 제14권2호
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• pp.137-141
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• 2010

We report, for the first time to our knowledge, observation of polarization bistability from 1.55-${\mu}m$ wavelength single-mode VCSELs of a conventional cylinder-shape under control of their driving current, and demonstration of all-optical flip-flop (AOFF) operations based on the bistability with optical set and reset pulse injection at a 50 MHz switching frequency. The injection pulse energy was less than 14 fJ. The average on-off contrast ratio of the flip-flopped signals was about 7 dB. These properties of the VCSELs will be potentially useful for future high-speed all-optical signal processing applications.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.347-350
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• 2000

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• ETRI Journal
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• 제36권6호
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• pp.942-952
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• 2014

This paper presents a novel test point insertion (TPI) method for a pseudo-random built-in self-test (BIST) to reduce the area overhead. Recently, a new TPI method for BISTs was proposed that tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving control points. The replacement rule used in a previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip-flops. This paper proposes a logic cone analysis-based TPI approach to overcome the limitations. Logic cone analysis is performed to find candidate functional flop-flops for replacing dedicated flip-flops. Experimental results indicate that the proposed method reduces the test point area overhead significantly with minimal loss of testability by replacing the dedicated flip-flops.

• 전자공학회논문지 IE
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• 제44권2호
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• pp.14-20
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• 2007

본 논문에서는 개선된 성능을 갖는 4치 D-플립플롭을 제안하였다. 제안된 4치 D 플립플롭은 뉴런모스를 기반으로 바이어스 인버터, 온도계 코드 출력회로, EX-OR 게이트, 전달 게이트를 이용하여 4치 항등 논리회로(Identity logic circuit)를 구성하고, 이를 2진의 RS 래치 회로와 결합하여 설계하였다. 설계된 회로들은 3.3V 단일 공급 전원에서 $0.35{\mu}m$ 1-poly 6-metal COMS 공정 파라미터 표준조건에서 HSPICE를 사용하여 모의실험 하였다. 모의실험 결과, 본 논문에서 제안된 4치 D 플립플롭은 100MHz 전후까지의 빠른 동작속도로 측정되었으며 PDP(Power dissipation-delay time product)와 FOM(Figure of merit)은 각각 59.3pJ과 33.7로 평가되어졌다.

• Progress in Superconductivity
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• 제5권1호
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• pp.13-16
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• 2003

In this work, we have studied about an RSFQ (Rapid Single Flux Quantum) switch element. The circuit was designed, simulated, and laid out for mask fabrication. The switch cell was composed of a D flip-flop, a splitter, a confluence buffer, and a switch core. The switch core determined if the input data could pass to the output. “On” and o“off” controls in the switch core could be possible by utilizing an RS flip-flop. When a control pulse was input to the “on” port, the RS flip-flop was in the set state and passed the input pulses to the output port. When a pulse was input to the “off” port, the RS flip-flop was in the reset state and prevented the input pulses from transferring to the output port. We simulated and optimized the switch element circuit by using Xic, WRspice, and Julia. The minimum circuit margins in simulations were more than $\pm$20%. We also performed the mask layout of the circuit by using Xic and Lmeter.

• 한국소프트웨어감정평가학회 논문지
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• 제15권1호
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• pp.103-107
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• 2019

최근 저전력 고속 디지털 데이터 통신을 구현 하기위해 많은 기술들이 개발되고 있는 추세이며 듀티사이클 보정에 관련된 기술도 그중 하나이다. 본 논문에서는 전압제어 링 발전기용 저-면적 듀티사이클 보정 회로를 제안하였다. 듀티사이클 보정 회로는 전압제어 링 발진기의 180도 위상차이를 이용하여 듀티사이클을 보정하는 회로이며, 제안된 저-면적 듀티사이클 회로는 기존의 플립플롭을 TSPC(True Single Phase Clocking) 플립플롭으로 변경하여 회로를 구성하였고 이로 인하여 저-면적 고성능 회로를 구현하였다. 일반적인 플립플롭을 대신하여 TSPC플립플롭을 사용하여 기존 회로 대비 저-면적으로 회로 구현이 가능하며 고속 동작에 용이하여 저-전력용 고성능 회로에 활용될 것으로 기대된다.

• 전자공학회논문지A
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• 제30A권7호
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• pp.75-81
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• 1993

In this paper, New type of Static Edge Triggered D Flip-Flop Circuits which are effective for the sequencial selecting and addressing of Matrix type Electrodes being applied to Flat Display Devices is proposed by the Design Technique using the Transmission Characteristics of Feedback Transistors and Charge Back Up Function. These Circuits composed of 2-4 less transistors in number than Conventional Static D Flip Flop's have some advantages that the Maximum Transition Time of Clock Signals allowed is increased by 100-450 times more than that of the Conventional circuit at 100KHz Clock Frequence and Circuit Safety is much increased by making the wider ranges, 1-4V, of Clock Levelas a Non-operating periods than 3-3.2V ranges in case of the Conventional Circuit at 10MHz clock frequence. By these advantages, These circuits can be very effectively used in case that clock signal has long transition time, especially on the low frequency operation.

• 한국초전도ㆍ저온공학회논문지
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• 제7권1호
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• pp.17-20
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• 2005

We has designed, fabricated, and measured a Single flux quantum (SFQ) toggle flip-flop (TFF). The TFF is widely used in superconductive digital electronics circuits. Many digital devices, such as frequency counter, counting ADC and program counter be used TFF Specially, a program counter may be constructed based on TFF We have designed the newly TFF and obtained high bias margins on test. In this work, we used two circuit simulation tools, WRspice and Julia, as circuit optimization tools. We used XIC for a layout tool. Newly designed TFF had minimum bias margins of +/- $37\%$ and maximum bias margins of +/-$37\%$(enhanced from +/- $37\%$). The designed circuits were fabricated by using Nb technology The test results showed that the re-optimized TFF operated correctly on 100kHz and had a very wide bias margins of +/- $53\%$.

• 대한전기학회논문지:전력기술부문A
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• 제48권9호
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• pp.1161-1166
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• 1999

Delay testing has become highlighted in the field of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan filp-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased by about 10% on the average.

• Current Optics and Photonics
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• 제4권5호
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• pp.405-410
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• 2020

A new all-optical flip-flop (AOFF) method based on the absorption nulls of an injection-locked Fabry-Perot laser diode (FP-LD) in transverse magnetic (TM) mode is proposed and experimentally demonstrated. For the set and reset operations of the AOFF, injection locking and the destructive minus of beating in transverse electric (TE) mode are used. The absorption nulls on the TM mode are modulated according to the operations, and then non-inverted (Q) and inverted (${\bar{Q}}$) outputs can be obtained simultaneously. Thanks to the use of several absorption nulls, the proposed AOFF can achieve multiple outputs with extinction ratios of more than 15 dB. Even though the experiment is demonstrated at 100 Mbit/s, the results of previous experiments using the injection of a CW holding beam imply that the operation speed can increase to 10 Gbit/s.