ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
권호 표지
DOI QR코드

DOI QR Code

Test Point Insertion with Control Point by Greater Use of Existing Functional Flip-Flops

  • Yang, Joon-Sung (Department of Semiconductor Systems Engineering, Sungkyunkwan University) ;
  • Touba, Nur A. (Department of Electrical and Computer Engineering, University of Texas at Austin)
  • Received : 2013.11.21
  • Accepted : 2014.03.05
  • Published : 2014.12.01
Download PDF
⟨ Previous Next ⟩

Abstract

This paper presents a novel test point insertion (TPI) method for a pseudo-random built-in self-test (BIST) to reduce the area overhead. Recently, a new TPI method for BISTs was proposed that tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving control points. The replacement rule used in a previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip-flops. This paper proposes a logic cone analysis-based TPI approach to overcome the limitations. Logic cone analysis is performed to find candidate functional flop-flops for replacing dedicated flip-flops. Experimental results indicate that the proposed method reduces the test point area overhead significantly with minimal loss of testability by replacing the dedicated flip-flops.

Keywords

References

  1. C. Barnhart et al., "OPMISR: The Foundation for Compressed ATPG Vectors," Proc. Int. Test Conf., Baltimore, MD, USA, Oct. 30, 2001, pp. 748-757.
  2. A. Jas, C.V. Krishna, and N.A. Touba, "Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning," IEEE Proc. VLSI Test Symp., Marina Del Rey, CA, USA, Apr. 29 - May 3, 2001, pp. 2-8.
  3. H. Ren et al., "Low-Cost TPI without Using Extra Registers for High Performance Design," Proc. Int. Test Conf., Austin, TX, USA, Nov. 1-6, 2009, pp. 1-8.
  4. M. Bershteyn, "Calculation of Multiple Sets of Weights for Weighted Random Testing," Proc. Int. Test Conf., Baltimore, MD, USA, Oct. 17-21, 1993, pp. 1031-1040.
  5. L. Lai et al., "Hardware Efficient LBIST with Complementary Weights," IEEE Proc. Int. Conf. Comput. Des., San Jose, CA, USA, Oct. 2-5, 2005, pp. 479-481.
  6. A. Paschalis, I. Voyiatzis, and D. Gizopoulos, "Accumulator Based 3-Weight Pattern Generation," IEEE Trans. Very Large Scale Integr. Syst., vol. 20, no. 2, Feb. 2012, pp. 357-361. https://doi.org/10.1109/TVLSI.2010.2102373
  7. I. Pomeranz and S.M. Reddy, "3-Weight Pseudo Random Test Generation Based on a Deterministic Test Set for Combinational and Sequential Circuits," IEEE Trans. Comput.-Aided Des. Integr. Circuites Syst., vol. 12, no. 7, July 1993, pp. 1050-1058. https://doi.org/10.1109/43.238041
  8. T. Enmin, S. Song, and Y. Zham "Weighted Test Generator in Built-in Self-Test Design Based on Genetic Algorithm and Cellular Automata," Int. Conf. Electron. Meas. Instrum., Chengdu, China, Aug. 16-19, 2011, pp. 134-138.
  9. V. Gherman et al., "Efficient Pattern Mapping for Deterministic Logic BIST," Proc. Int. Test Conf., Charlotte, NC, USA, Oct. 26-28, 2004, pp. 48-56.
  10. N.A. Touba and E.J. McCluskey, "Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST," Proc. Int. Test Conf., Washington, DC, USA, Oct. 21-25, 1995, pp. 674-682.
  11. H.-J. Wunderlich et al., "Efficient Pattern Mapping for Deterministic Logic BIST," IEEE Proc. VLSI Test Symp., Charlotte, NC, USA, Oct. 26-28, 2004, pp. 48-56.
  12. W. Li et al., "A Scan BIST Generation Method Using a Markov Source and Partial Bit-Fixing," Proc. Des. Autom. Conf., Anaheim, CA, USA, June 2-6, 2003, pp. 554-559.
  13. H.-J. Wunderlich and G. Kiefer, "Bit-Flipping BIST," Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., San Jose, CA, USA, Nov. 10-14, 1996, pp. 337-343.
  14. S. Hellebrand et al., "Built-in Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," IEEE Trans. Comput., vol. 44, no. 2, Feb. 1995, pp. 223-233. https://doi.org/10.1109/12.364534
  15. H.-S. Kim and S. Kang, "Increasing Encoding Efficiency of LFSR Reseeding-Based Test Compression," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 25, no. 5, May 2006, pp. 913-917. https://doi.org/10.1109/TCAD.2005.855977
  16. X. Kavousianos et al., "Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-At Test Sets," IEEE Trans. Very Large Scale Integr. Syst., vol. 19, no. 12, Dec. 2011, pp. 2330-2335. https://doi.org/10.1109/TVLSI.2010.2079961
  17. J. Lee and N.A. Touba, "LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 26, no. 2, Feb. 2007, pp. 396-401. https://doi.org/10.1109/TCAD.2006.882509
  18. J. Rajski et al., "Embedded Deterministic Test for Low Cost Manufacturing Test," Proc. Int. Test Conf., Washington, DC, USA, 2002, pp. 301-310.
  19. Z. Wang et al., "Deviation-Based LFSR Reseeding for Test-Data Compression," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 28, no. 2, Feb. 2009, pp. 259-271. https://doi.org/10.1109/TCAD.2008.2009166
  20. E.B. Eichelberger and E. Lindbloom, "Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test," IBM J. Res. Develop., vol. 27, no. 3, May 1983, pp. 265-272. https://doi.org/10.1147/rd.273.0265
  21. N.Z. Basturkmen, S.M. Reddy, and J. Rajski, "Improved Algorithms for Constructive Multi-phase TPI for Scan Based BIST," Proc. Asia South Pacific Des. Autom. Conf., Bangalore, India, Jan. 7-11, 2002, pp. 604-611.
  22. Semiconductor Industry Association. The Int. Technol. Roadmap for Semicond., 2007.
  23. K.-T. Cheng and C.-J. Lin, "Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST," Proc. Int. Test Conf., Washington, DC, USA, Oct. 21-25, 1995, pp. 506-514.
  24. H.-C. Tsai et al., "Efficient Test Point Selection for Scan-Based BIST," IEEE Trans. VLSI Syst., vol. 6, no. 4, Dec. 1998, pp. 667-676. https://doi.org/10.1109/92.736140
  25. R. Haoxing et al., "Low Cost TPI without Using Extra Registers for High Performance Design," Proc. Int. Test Conf., Austin, TX, USA, Nov. 1-6, 2009, pp. 1-8.
  26. M. Nakao et al., "Low Overhead Test Point Insertion for Scan-Based BIST," Proc. Int. Test Conf., Atlantic City, NJ, USA, Sept. 28-30, 1999, pp. 384-357.
  27. R. Sethuram et al., "Zero-Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured Asics," Proc. Asian Test Symp., Fukuoka, Japan, Nov. 20-23, 2006, pp. 339-348.
  28. N. Tamarapalli and J. Rajski "Constructive Multi-phase Test Point Insertion for Scan-Based BIST," Proc. Int. Test Conf., Washington, DC, USA, Oct. 20-25, 1996, pp. 649-658.
  29. J.-S. Yang, B. Nadeau-Dostie, and N.A. Touba, "Test Point Insertion Using Functional Flip-Flops to Drive Control Points," Proc. Int. Test Conf., Austin, TX, USA, Nov. 1-6, 2009, pp. 1-10.
  30. J.-S. Yang, N.A. Touba, and B. Nadeau-Dostie, "Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops," IEEE Trans. Comput., vol. 10, no. 10, Oct. 2012, pp. 1473-1483.
  31. J.-S. Yang, B. Nadeau-Dostie, and N.A. Touba, "Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points," Proc. IEEE Symp. Defect Fault Tolerance VLSI Syst., Chicago, IL, USA, Oct. 7-9, 2009, pp. 20- 28.
  32. OPENCORES. Accessed Oct. 21, 2008. http://www.opencores.org
  33. J.-S. Yang and N.A. Touba, "Automated Selection of Signals to Observe for Efficient Silicon Debug," Proc. VLSI Test Symp., Santa Cruz, CA, USA, May 3-7, 2009, pp. 79-84.
  34. W. Jang and D.Z. Pan, "Application-Aware NOC Design for Efficient SDRAM Access," IEEE Trans. Comput.-Aided Des. Integr Circuits Syst., vol. 30, no. 10, Oct. 2011, pp. 1521-1533. https://doi.org/10.1109/TCAD.2011.2160176
  35. Mentor Graphics Tessent Tools Reference Manual, 2010.
  36. Synopsys Design Compiler, A-2007.12-SP4.