• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.158-158
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• 2008

모바일 정보통신기기를 중심으로 실장모듈의 초소형화, 고집적화로 인해 접속단자의 피치가 점점 미세화 됨에 따라 플립칩 본딩용 접착제에 함유되는 무기충전제인 실리카 필러의 크기도 미세화되고 있다. 본 연구에서는 NCP (non-conductive paste)의 실리카 필러의 크기가 COB(chip-on-board) 플립칩 패키지의 신뢰성에 미치는 영향을 조사하였다. 실험에 사용된 실리카 필러는 Fused silica 3 종과 Fumed silica 3종이며 response surface 실험계획법에 따라 혼합하여 최적의 혼합비를 정하였다. 테스트베드로 사용된 실리콘 다이는 투께 $700{\mu}m$, 면적 5.2$\times$7.2mm로 $50\times50{\mu}m$ 크기의 Au 도금범프를 $100{\mu}m$ 피치, peripheral 방식으로 형성시켰으며, 기판은 패드를 Sn으로 finish 하였다. 기판을 플라즈마 전처리 후 Panasonic FCB-3 플립칩 본더를 이용하여 플립칩 본딩을 수행하였다. 패키지의 신뢰성 평가를 위해 $-40^{\circ}C{\sim}80^{\circ}C$의 열충격시험과 $85^{\circ}C$/85%R.H.의 고온고습시험을 수행하였으며 Die shear를 통한 접합 강도와 4-point probe를 통한 접속저항을 측정하였다.

• 마이크로전자및패키징학회지
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• 제17권2호
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• pp.21-28
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• 2010

본 논문에서는 온도 사이클이 진행되는 동안 비선형 거동과 크립 거동을 보이는 FC-PBGA 패키지 솔더볼의 변형거동을 알아보기 위하여 시간에 종속하는 거동을 적용 시킬 수 있는 점소성 모델과 크립 모델에 대하여 유한요소해석을 수행하였다. 유한요소해석 결과의 신뢰성을 평가하기 위하여 무아레 간섭계를 이용하여 온도변화에 따른 열변형 실험을 수행하였다. 전체적인 굽힘변위는 Anand 모델과 변형률 분리 모델 모두 실험결과와 잘 일치하였으나 솔더볼의 변형률은 Anand 모델의 경우 큰 차이를 보이고 변형률 분리 모델의 경우 상당히 일치하는 계산결과를 얻었다. 따라서 본 논문에서는 변형률 분리 모델을 이용하여 시간에 종속하는 FC-PBGA 패키지 솔더볼의 크립 거동을 검토하였다. 솔더를 포함한 패키지에 온도변화가 생길 때 고온에서는 시간이 지남에 따라 크립 거동에 의해 솔더의 응력이 점차 완화되는 현상을 나타내고 있음을 알 수 있었다.

• 반도체디스플레이기술학회지
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• 제17권4호
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• pp.42-45
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• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.

• 마이크로전자및패키징학회지
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• 제26권2호
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• pp.31-43
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• 2019

본 연구에서는 유연한 접속부를 갖는 유연전자 패키지 플립칩 접속을 위해 폴리머 탄성범프를 제작하였으며, 범프의 온도 및 하중에 따른 폴리머 탄성 범프의 점탄성 및 점소성 거동을 해석 및 실험적으로 분석하고 비교 평가하였다. 폴리머 탄성 범프는 하중에 의한 변형이 용이하여 범프 높이 평탄도 오차의 보정이 용이할 뿐만 아니라 소자가 형성된 칩에 가해지는 응력 집중이 감소하는 것을 확인하였다. 폴리머 탄성 범프의 과도한 변형에 따른 Au Metal Cap Crack 현상을 보완하여 $200{\mu}m$ 직경의 Spiral Cap Type, Spoke Cap type 폴리머 탄성 범프 형성 기술을 개발하였다. 제안된 Spoke Cap, Spiral Cap 폴리머 탄성 범프는 폴리머 범프 전체를 금속 배선이 덮고 있는 Metal Cap 범프에 비해 범프 변형에 의한 응력 발생이 적음을 확인할 수 있으며 이는 폴리머 범프 위의 금속 배선이 부분적으로 패터닝되어 있어 쉽게 변형될 수 있는 구조이므로 응력이 완화되는데 기인하는 것으로 판단된다. Spoke cap type 범프는 패드 접촉부와 전기적 접속을 하는 금속 배선 면적이 Spiral Cap type 범프에 비해 넓어 접촉 저항을 유지하면서 동시에 금속 배선에 응력 집중이 가장 낮은 결과를 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.366-369
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• 2003

The vertical fountain plating system with the point contact has been used in semiconductor industry. But the plating shape in the opening of photoresist becomes gradated shape, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. So, we designed the tilted electrode ring contact to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and $\alpha$-step. A photoresist was coated to a thickness of $60{\mu}m$ and vias were patterned by a contact aligner After via opening, solder layer was electroplated using the fountain plating system and the tilted electrode ring contact system. In $\alpha$-step measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were ${\pm}16%,\;{\pm}3.7%$ respectively. In this study, we could get high uniformity bumps by the tilted electrode ring contact system. So, tilted electrode ring contact system is expected to improve workability and yield in module process.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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• pp.233-241
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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• pp.211-219
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• 마이크로전자및패키징학회지
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• 제23권2호
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• pp.79-84
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• 2016

유연전자소자가 외부힘에 의해 변형될 경우 반도체 다이가 기계적 응력 때문에 변형되거나 파괴되고 이러한 변형이나 파괴는 channel의 전자이동도를 변화시키거나 배선의 저항을 증가시켜 집적회로의 동작 오류를 발생시킨다. 따라서 반도체 집적회로는 굽힘 변형이 발생해도 기계적 응력이 발생하지 않는 중립축에 위치하는 것이 바람직하다. 본 연구에서는 굽힘변형을 하는 flip-chip 접합공정이 적용된 face-down flexible packaging system에서 중립축의 위치와 파괴 모드를 조사하였고 반도체 집적회로와 집중응력이 발생한 곳의 응력을 감소시킬 수 있는 방법을 제시하였다. 이를 위해, 설계인자로 유연기판의 두께 및 소재, 반도체 다이의 두께를 고려하였고 설계인자가 중립축의 위치에 미치는 영향을 조사한 결과 유연기판의 두께가 중립축의 위치를 조절하는데 유용한 설계인자임을 알 수 있었다. 3차원 모델을 이용한 유한요소해석 결과 반도체 다이와 유연기판 사이의 Cu bump 접합부에서 항복응력보다 높은 응력이 인가될 수 있음을 확인하였다. 마지막으로 flexible face-down packaging system에서 반도체 다이와 Cu bump 의 응력을 감소시킬 수 있는 설계 방법을 제안하였다.

• 마이크로전자및패키징학회지
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• 제26권4호
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• pp.55-62
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• 2019

Polydimethylsiloxane (PDMS)를 베이스 기판으로 사용하고 이보다 강성도가 높은 flexible printed circuit board (FPCB)를 island 기판으로 사용한 soft PDMS/hard PDMS/FPCB 구조의 강성도 경사형 신축패키지를 형성하고, 이의 탄성특성 및 인장 싸이클과 굽힘 싸이클에 따른 신뢰성을 분석하였다. Soft PDMS, hard PDMS, FPCB의 탄성계수가 각기 0.28 MPa, 1.74 MPa, 2.25 GPa일 때 soft PDMS/hard PDMS/FPCB 신축패키지의 유효 탄성계수는 0.6 MPa로 분석되었다. 0~0.3 범위의 인장 싸이클을 15,000회 인가시 신축패키지의 저항변화률은 2.8~4.3% 이었으며, 굽힘반경 25 mm의 굽힘 싸이클을 15,000회 인가시 저항변화률은 0.9~1.5% 이었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.242-242
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• 2006

Increasingly complex tasks are performed by computers or cellular phone, requiring more and more memory capacity as well as faster and faster processing speeds. This leads to a constant need to develop more highly integrated circuit systems. Therefore, there have been numerous studies by many engineers investigating circuit patterning. In particular, PCB including module/package substrates such as FCB (Flip Chip Board) has been developed toward being low profile, low power and multi-functionalized due to the demands on miniaturization, increasing functional density of the boards and higher performances of the electric devices. Imprint lithography have received significant attention due to an alternative technology for photolithography on such devices. The imprint technique. is one of promising candidates, especially due to the fact that the expected resolution limits are far beyond the requirements of the PCB industry in the near future. For applying imprint lithography to FCB, it is very important to control thermal properties and mechanical properties of dielectric materials. These properties are very dependent on epoxy resin, curing agent, accelerator, filler and curing degree(%) of dielectric materials. In this work, the epoxy composites filled with silica fillers and cured with various accelerators having various curing degree(%) were prepared. The characterization of the thermal and mechanical properties wasperformed by thermal mechanical analysis (TMA), thermogravimetric analysis (TGA), differential scanning calorimetry (DSC), rheometer, an universal test machine (UTM).