• Journal of the Korea Society of Computer and Information
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• v.20 no.2
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• pp.1-10
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• 2015

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.51-58
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• 2004

Most of pubic-key cryptosystems are built on the basis of arithmetic operations defined over the finite field GF$GF(2^m)$ .The other operations of finite fields except addition can be computed by repeated multiplications. Therefore, it is very important to implement the multiplication operation efficiently in public-key cryptosystems. We propose an efficient bit-parallel normal basis multiplier for$GF(2^m)$ fields defined by All-One Polynomials. The gate count and time complexities of our proposed multiplier are lower than or equal to those of the previously proposed multipliers of the same class. Also, since the architecture of our multiplier is regular, it is suitable for VLSI implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.628-636
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• 2010

In this paper, we present a new type high speed parallel multiplier for performing the multiplication of two polynomials using standard basis in the finite fields GF($2^m$). Prior to construct the multiplier circuits, we design the basic cell of vector code generator(VCG) to perform the parallel multiplication of a multiplicand polynomial with a irreducible polynomial and design the partial product result cell(PPC) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial with VCG circuits. The presented multiplier performs high speed parallel multiplication to connect PPC with VCG. The basic cell of VCG and PPC consists of one AND gate and one XOR gate respectively. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields GF($2^4$). Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper uses the VCGs and PPCS repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSL.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1209-1217
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• 2008

In this paper, we present a new bit-parallel multiplier for performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the vector code generator(VCG) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of VCG have two AND gates and two XOR gates. Using these VCG, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the VCGs with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• Honam Mathematical Journal
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• v.29 no.3
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• pp.415-425
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• 2007

The normal basis has the advantage that the result of squaring an element is simply the right cyclic shift of its coordinates in hardware implementation over finite fields. In particular, the optimal normal basis is the most efficient to hardware implementation over finite fields. In this paper, we propose an efficient parallel architecture which transforms the Gaussian normal basis multiplication in GF($2^m$) into the type-I optimal normal basis multiplication in GF($2^{mk}$), which is based on the palindromic representation of polynomials.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.227-233
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• 2016

Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for $GF(2^m)$ fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.6
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• pp.17-28
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• 2002

XTR is a new method to represent elements of a subgroup of a multiplicative group of a finite field GF( $p^{6m}$) and it can be generalized to the field GF( $p^{6m}$)$^{[6,9]}$ This paper progress optimal extention fields for XTR among Galois fields GF ( $p^{6m}$) which can be aplied to XTR. In order to select such fields, we introduce a new notion of Generalized Opitimal Extention Fields(GOEFs) and suggest a condition of prime p, a defining polynomial of GF( $p^{2m}$) and a fast method of multiplication in GF( $p^{2m}$) to achieve fast finite field arithmetic in GF( $p^{2m}$). From our implementation results, GF( $p^{36}$ )longrightarrowGF( $p^{12}$ ) is the most efficient extension fields for XTR and computing Tr( $g^{n}$ ) given Tr(g) in GF( $p^{12}$ ) is on average more than twice faster than that of the XTR system on Pentium III/700MHz which has 32-bit architecture.$^{［6,10］/ ［6,10］/6,10］}$

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.4
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• pp.409-416
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• 2014

In H/W implementation for the finite field, the use of normal basis has several advantages, especially the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. The finite field $GF(2^m)$ with type I optimal normal basis(ONB) has the disadvantage not applicable to some cryptography since m is even. The finite field $GF(2^m)$ with type II ONB, however, such as $GF(2^{233})$ are applicable to ECDSA recommended by NIST. In this paper, we propose a bit-parallel multiplier over $GF(2^m)$ having a type II ONB, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{2m})$. The time and area complexity of the proposed multiplier is the same as or partially better than the best known type II ONB bit-parallel multiplier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.235-239
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• 1989

A multiplier is proposed for computing multiplication of two arbitrary elements in the finite fields GF($2^m$), and the operation process is described step by step. The modified type of the circuit which is constructed with m-stage feedgack shift register, m-1 flip-flop, m AND gate, and m-input XOR gate is presented by referring to the conventional shift-register multiplier. At the end of mth shift, the shift-register multiplier stores the product of two elements of GF($2^m$); however the proposed circuit in this paper requires m-1 clock times from first input to first output. This circuit is simpler than cellulra-array or systolic multiplier and moreover it is faster than systolic multiplier.