Journal of the Korea Society of Computer and Information (한국컴퓨터정보학회논문지)

Korean Society of Computer Information (한국컴퓨터정보학회)
권호 표지
DOI QR코드

DOI QR Code

Design of High-Speed Parallel Multiplier on Finite Fields GF(3m)

유한체 GF(3m)상의 고속 병렬 곱셈기의 설계

  • Received : 2014.12.30
  • Accepted : 2015.01.21
  • Published : 2015.02.28
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

본 논문에서는 유한체 $GF(3^m)$상에서 모든 항에 0이 아닌 계수를 갖는 기약 다항식에 대하여 m이 홀수 및 짝수인 경우 $GF(3^m)$상의 곱셈 알고리즘을 제시하였으며, 제시한 곱셈 알고리즘을 이용하여 고속의 병렬 입-출력 모듈구조의 곱셈기를 설계하였다. 제시한 곱셈기의 구성은 $(m+1)^2$개의 동일한 기본 셀들로 설계되었으며, 셀에 메모리를 사용하지 않았으므로 회로가 간단하며 셀당 $T_A+T_X$의 지연시간을 갖는다. 본 논문에서 제안한 곱셈기는 규칙성과 셀 배열에 의한 모듈성을 가지므로 m이 큰 회로의 확장이 용이하며 VLSI회로 실현에 적합할 것이다.

Keywords

References

  1. K. C. Smith. "The Prospect for Multivalued Logic : A Technology and Applications View," IEEE Trans. Computers, Vol. C-30, No. 9, pp. 619-634, Sept. 1981. https://doi.org/10.1109/TC.1981.1675860
  2. M. Kameyama and T. Higuchi, "Multiple-Valued Logic and Special Purpose Processors : Overview and Future," in Proc. IEEE Int. Symp. Multiple-Valued Logic, pp. 289-292, 1982.
  3. S .L. Hurst, "Multiple-valued Logic-its Future," IEEE Trans. Computers, Vol 30, pp. 1161-1179, Dec. 1984.
  4. M. A. Hasan, M. Wang, and V. K. Bhargava, "Moduler Construction of Low Complexity Parallel Multipliers for a Class of Finite Fields $GF(2^m)$," IEEE Trans. Computers, Vol. 41, No. 8, pp. 961-971, Aug. 1992.
  5. 3rd Generation Partnership Project., "Technical specification group GSM/EDGE radio access network; channel coding (release 5)," Tech. Rep. 3GPP TS 45.003 V5.6.0, June 2003.
  6. C. K. Koc, and B. Sunar, "Low Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields," IEEE Trans. Computers, Vol. 47, No. 3, pp. 353-356, Mar. 1998. https://doi.org/10.1109/12.660172
  7. A. Halbutogullari and C. K. Koc, "Mastrovito Multiplier for General Irreducible Polynomials," IEEE Trans. Computers, Vol. 49, No. 5, pp. 503-518, May 2000. https://doi.org/10.1109/12.859542
  8. C. Y. Lee, E. H. Lu, and J. Y. Lee, "Bit Parallel Systolic Multipliers for $GF(2^m)$ Fields Defined by All-One and Equally Spaced Polynomials," IEEE Trans. Computers, Vol. 50, No. 5, pp. 385-392, May 2001. https://doi.org/10.1109/12.926154
  9. T. W. Kim, W. J. Lee, and K. W. Kim, "Bit-Parallel Systolic Multiplication Architecture with Low Complexity and Latency in $GF(2^m)$ Using Irreducible AOP," Journal of KIIT, Vol. 11, No. 3, pp. 133-139, March 2013.
  10. K. W. Kim and J. C. Jeon, "Montgomery Multiplication Architecture Based on Cellular Systolic Array over $GF(2^m)$," Journal of KIIT, Vol. 10, No. 9, pp. 1-6, Sept. 2013.
  11. N. S Chang, T. H. Kim, C. H. Kim, D. G. Han, and H. W. Kim, "Digit-Serial Finite Field Multipliers for $GF(2^m)$," Journal of IEIE, Vol. 45-SD, No. 10, pp. 23-30, Oct. 2008.
  12. C. L. Wang and J. L. Lin, "Systolic Array Implementation of Multipliers for Finite Fields $GF(2^m)$," IEEE Trans. Circuits and Systems, Vol. 38, No. 7, July 1991.
  13. S. W. Wei, "A Systolic Power-Sum Circuit for $GF(2^m)$," IEEE Trans. Computers, Vol. 43, No. 2, pp. 226-229, Feb. 1994. https://doi.org/10.1109/12.262128