• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.823-826
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• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.

• Nuclear Engineering and Technology
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• 제49권8호
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• pp.1589-1599
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• 2017

Field programmable gate arrays (FPGAs) are getting more attention in safety-related and safety-critical application development of nuclear power plant instrumentation and control systems. The high logic density and advancements in architectural features make static random access memory (SRAM)-based FPGAs suitable for complex design implementations. Devices deployed in the nuclear environment face radiation particle strike that causes transient and permanent failures. The major reasons for failures are total ionization dose effects, displacement damage dose effects, and single event effects. Different from the case of space applications, soft errors are the major concern in terrestrial applications. In this article, a review of radiation effects on FPGAs is presented, especially soft errors in SRAM-based FPGAs. Single event upset (SEU) shows a high probability of error in the dependable application development in FPGAs. This survey covers the main sources of radiation and its effects on FPGAs, with emphasis on SEUs as well as on the measurement of radiation upset sensitivity and irradiation experimental results at various facilities. This article also presents a comparison between the major SEU mitigation techniques in the configuration memory and user logics of SRAM-based FPGAs.

• 한국정보통신학회논문지
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• 제21권3호
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• pp.601-606
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• 2017

고성능 디지털 회로 개발과 구현에 사용되는 SRAM 기반 FPGA(Field Programmable Gate Array)는 configuration memory가 SRAM으로 구현되었기 때문에 configuration memory에 소프트 에러가 발생하는 경우 오동작하게 된다. Xilinx사의 FPGA는 configuration memory 영역에 추가된 ECC(Error Correction Code)와 CRC(Cyclic Redundancy Code) 그리고 이들을 활용하는 SEM(Soft Error Mitigation) Controller를 이용하여 이러한 소프트 에러의 영향을 줄일 수 있다. 본 연구에서는 SRAM 기반 FPGA에서 SEM Controller에 의해 configuration memory 영역이 소프트 에러로부터 보호될 때 FPGA의 신뢰도를 가용성 관점에서 해석하고 그 효과를 분석하였다. 이를 위해 FPGA 계열별 SEM Controller의 소프트 에러 정정 성능에 따른 가용성 함수를 유도하고 FPGA 계열별 사례를 적용하여 비교하였다. 연구 결과는 SRAM 기반 FPGA의 선정 및 가용성 예측에 활용될 수 있을 것으로 기대된다.

• Nuclear Engineering and Technology
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• 제55권8호
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• pp.2952-2965
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• 2023

Advanced reactors, such as Small Modular Reactors or existing Nuclear Power Plants, often use Field Programmable Gate Array (FPGA) based controllers in new Instrumentation and Control (I&C) system architectures or as an alternative to existing analog-based I&C systems. Compared to CPU-based Programmable Logic Controllers (PLCs), FPGAs offer better overall performance. However, programming functions on FPGAs can be challenging due to the requirement for a hardware description language that does not explicitly support the operation of real numbers. This study aims to implement the Reactor Trip (RT) functions of the existing analog-based Reactor Protection System (RPS) using FPGAs. The RT equations for Overtemperature delta Temperature and Overpower delta Temperature involve dynamic compensators expressed with the Laplace transform variable, 's', which is not directly supported by FPGAs. To address this issue, the trip equations with the Laplace variable in the continuous-time domain are transformed to the discrete-time domain using the Z-transform. Additionally, a new operation based on a relative value for the equation range is introduced for the handling of real numbers in the RT functions. The proposed approach can be utilized for upgrading the existing analog-based RPS as well as digitalizing control systems in advanced reactor systems.

• 컴퓨터교육학회논문지
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• 제16권3호
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• pp.99-105
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• 2013

ASIC설계에서 FPGA를 이용한 에뮬레이션은 설계 검증을 위한 필수 단계이다. ASIC으로 설계된 모델을 가능한 최대 동작주파수로 에뮬레이션하기 위해서는 FPGA의 특성을 이해해야 한다. 본 논문은 FPGA의 주요 제조사인 Xilinx와 Altera의 여러 디바이스에 다양한 가산기와 MIPS CPU를 포팅하여, 디자인 복잡도에 따른 현대 FPGA의 특성을 연구하였다. 실험 결과, 일반적인 통념과는 다르게 1-bit 가산기를 기반으로 디자인한 RCA는 FPGA 내부의 carry-chain을 활용하지 못했고, 그 결과 다른 타입의 가산기보다 낮은 성능을 보였다. 또한, 본 연구를 통해 Xilinx와 Altera 제조사 별 FPGA 특성에 확연한 차이가 있음을 확인하였다. 즉, 동작속도에 최적화하여 설계된 Prefix 가산기를 Xilinx 디바이스에 포팅했을 때 저조한 동작주파수를 보였으나, Altera 디바이스에서는 IP Core와 비슷한 성능을 보였다. 이는 Altera 디바이스에서는 FPGA의 면적만 허락한다면 ASIC에 최적화된 설계를 그대로 사용하여도 에뮬레이션 성능에 영향을 미치지 않음을 시사한다. MIPS CPU를 통한 실험은 이를 뒷받침한다.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2003년도 봄 학술발표논문집 Vol.30 No.1 (B)
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• pp.283-285
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• 2003

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAS. Field programmable gate array(FPGAS) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific Integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAS are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1276-1279
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• 2002

In order to satisfy the requirement for various applications in an electronic device, many dynamically reconfigurable systems such as FPGAs have been used recently. This paper presents a pipelined scheduling for dynamically reconfigurable systems based on FPGAs. For reconfigurable systems conventional schedulings have reduced processing time by minimizing the number of reconfigurations. However, they are not effective enough for applications including many iterative processes such as digital signal processing. Our approach has been able to increase throughput of iterative applications on dynamically reconfigurable systems by using pipelined scheduling.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1161-1164
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• 2003

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array(FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.70-73
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• 2004

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array (FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2002년도 가을 학술발표논문집 Vol.29 No.2 (1)
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• pp.721-723
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• 2002

본 논문에서는 최근 수요가 급격히 증가하고 있는 FPGA의 전력 소모 특성을 분석하기 위해서 개발한 측성 시스템(SECF : Seoul National University Energy Characterizer FPGAs)의 구성 및 동작 방법을 설명하고 있다. 또한 이 시스템을 이용하여 몇 가지의 간단한 실험을 통해 FPGA 전력 소모 경향을 살펴보는 것을 그 목적으로 한다.