• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2071-2077
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• 2010

Interface modules design between image sensor and external components are designed by FPGA (Field Programmable Gate Array) in this paper. Generally speaking, to satisfy synchronization for the poor quality data in image, SRAM is needed. To receive synchronization signal and image signal data with pixel dimension, the proposed interface logic technique is implemented. From the proposed technique, we can obtain more clear screen by implementing with pixel dimension. Operating frequency of image sensor and that of TFT-LCD are 50MHz and 6.5MHz, respectively. Most of control logic functions are embedded in FPGA. The designed logic gate counter has 33,216 and is designed by Quartus II.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.669-679
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• 2013

This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.635-637
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• 2013

This paper proposed a new hardware architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA environment, and has the performance of 813fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.999-1007
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• 2002

In this paper, the operation of matched filter for searching initial synchronization in direct sequence spread spectrum receiver is studied. The implementation model of the matched filter by HDL (Hardware Description Language) is proposed. The model has an architecture based on parallelism and pipeline for fast processing, which includes circular buffer, multiplier, adder, and code look-up table. The performance of the model is analyzed and compared with the implementation by a conventional digital signal processor. It is implemented on a FPGA (Field Programmable Gate Array) and its operation is validated in a timing simulation result.

• Journal of Broadcast Engineering
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• v.19 no.5
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• pp.616-626
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• 2014

In this paper, we introduce a real-time stereo-to-multiview conversion system using FPGA and GPU. The system is based on two different devices so that it consists of two major blocks. The first block is a disparity estimation block that is implemented on FPGA. In this block, each disparity map of stereoscopic video is estimated by DP(dynamic programming)-based stereo matching. And then the estimated disparity maps are refined by post-processing. The refined disparity map is transferred to the GPU device through USB 3.0 and PCI-express interfaces. Stereoscopic video is also transferred to the GPU device. These data are used to render arbitrary number of virtual views in next block. In the second block, disparity-based view interpolation is performed to generate virtual multi-view video. As a final step, all generated views have to be re-arranged into a single image at full resolution for presenting on the target autostereoscopic 3D display. All these steps of the second block are performed in parallel on the GPU device.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.145-151
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• 2004

For wide-band spread spectrum communication systems such as IMT-2000, a digital matched filter is a key device for rapid spreading code synchronization. Although a digital matched filter can be implemented easily, large power consumption at the higher chip rate and large summation delay of longer chip length are the bottleneck of practical use. In this paper, we propose a optimized partial correlation digital matched filter structure which can be constructed of the so-called generalized hierarchical Golay sequence. a partial correlation structure can reduce the number of correlators, but enlarge the size of flip-flops. In this paper, The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. A proposed digital matched filter reduce the size of flip-flops by rounding method. and it reduces about 45 percentages of power dissipation and chip area as compared with digital matched filter which is not rounded. rounding. The proposed architecture was verified by using Xilinx FPGA.

• Proceedings of the KIEE Conference
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• summer
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• pp.325-326
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• 2004

전력선통신(PLC: Power Line Communication)은 기존의 전기선을 이용하여 별도의 전용선 설치 없이 통신이 가능한 기술로서 효율적인 PLC 통신을 위해서는 가장 기본적인 기저대역의 송, 수신부상 의 원활한 데이터 전송이 이루어져야 한다. 본 논문에서는 확산대역방식의 PLC통신시스템의 수신부의 핵심모듈인 정합필터를 HDL(hardware description language)을 이용한 디지털 하드웨어인 에 위한 디지털 하드웨어인 FPGA(Field Programmable Gate Array)클 이용하여 구현하였다. 즉, 본 논문에서는 BPSK(Binary Phase Shift Keying) 변조 및 256칩 확산코드를 이용한 확산변조파형에 대한 디지털 정합필터를 FPGA로 구현하고 상관특성을 확인함으로서 모의실험상의 파형과 구현된 하드웨어상의 상관파형이 일치함을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.5B
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• pp.429-436
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• 2011

The G-PON is an efficient solution to implement the FTTH and have GEM frame to accomodate various protocols like Ethernet frames, IP packets, and TDM signals. Above all, the Ethernet is one of the most widely used 2nd layer protocol in the campus, the subscriber access, and the carrier service. So G-PON system has to provide an Ethernet interface with top priority. In this paper, we implement a gigabit Ethernet adapter based on Ethernet over GEM in the ITU-T G.984.3 to accommodate Ethernet protocol in the G-PON TC chip. The adapter maps each Ethernet frame to a single or multiple GEM frames and has several functions including generation of the GEM header, encapsulation of frames and the SAR. In particular, the adapter have converter (LUT) MAC address to port-ID which is a key to identify logical connections though it is not defined in specification but important. We implement the adapter with a FPGA and verify the functions of segmentation and reassembling, MAC address learning, and throughput with the logic analyzer and the Ethernet analyzer.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.11
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• pp.28-36
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• 1998

In the CDMA mobile communication system with asynchronous mode among base stations, the initial PN code acquisition method using a matched filter can be considered for the rapid PN code synchronization acquisition in the handoff region. In the model of the noncoherent QPSK/DS-SS under the Rayleigh fading channel, the mean acquisttion time of the matched filter is analyzed to have a shortened time in proportion to the length of matched filter to be compared with the serial correlation method. In this paper to improve the HW complexity of the conventional matched device which enables the repeated correlation process, is designed and its function is verified through the FPGAsimulation using Altera MaxPlus Ⅱ.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.4
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• pp.10-21
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• 2003

Recently, the optical subscriber interface module uses the high performance network processor to quickly develop new application services such as MPLS, VPN, RPR and EPON with a short time-to-market. Although a number of vendors are developing the network processor at 2.5Gbps, only the IBM NP4GS3 can provide packet processing with wire-speed at 2.5Gbps. IBM NP4GS3, however, uses its unique speed DASL interface instead of CSIX-Ll interface, which has standardized by M: Forum currently Therefore, we implement an interconnection mechanism to use the switch fabric with CSIX-Ll interface. In this paper, we suggest the architecture and a packet control mechanism supporting interconnection between IBM NP4GS3 DASL and CSIX-Ll switch interface using the common IBM UDASL ASIC and XILINX FPGA.