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High-Performance VLSI Architecture for Stereo Vision

스테레오 비전을 위한 고성능 VLSI 구조

  • Received : 2013.03.07
  • Accepted : 2013.08.14
  • Published : 2013.09.30

Abstract

This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

본 논문에서는 실시간으로 스테레오 정합을 수행하기 위한 VLSI(Very Large Scale Integrated Circuit)구조를 제안한다. 스테레오 정합의 연산을 분석하여 중간 연산 결과를 재사용하여 연산량과 메모리 접근수를 최소화한다. 이러한 동작을 수행할 수 있는 스테레오 정합 연산 셀의 구조를 제안하고, 이를 병렬적으로 확장하여 탐색 범위 내의 모든 비용함수를 동시에 연산할 수 있는 하드웨어의 구조를 제안한다. 이러한 하드웨어 구조를 확장하여 2차원 영역에 대한 비용함수를 연산할 수 있는 하드웨어의 구조와 동작을 제안한다. 구현한 하드웨어는 FPGA(Field Programmable Gate Array) 환경에서 최소 250Mhz의 클록 주파수에서 동작이 가능하고, 64화소의 탐색범위를 적용한 경우에 $640{\times}480$ 스테레오 영상을 약 805fps의 성능으로 처리할 수 있다.

Keywords

References

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