• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.11
• /
• pp.105-113
• /
• 2004

This paper proposes 3D graphics accelerator, especially rendering unit, for portable devices. The existing 3D architecture is not suitable for portable devices because of its huge size. To reduce the size, we use iterative architecture and fixed-point calculation. In this paper, we suggest the format of fixed-point comparing with the result images, and some special technique to control. Finally, it is implemented with FPGA and 0.25um ASIC technology respectively. The ASIC chip can execute 47.88M pixels per second. The size of ASIC chip is 4.9287mm*4.9847mm and the power consumption is 263.7mW with 50MHz operation frequency.

• Proceedings of the KIEE Conference
• /
• 2001.11c
• /
• pp.380-382
• /
• 2001

This paper presents the implementation of IEEE 802.11 Medium Access Control and Physical Layer Protocol that can be applied to wireless LAN system. We have used PRISM2 chipsets from Intersil to build the baseband, IF, and RF parts. DSSS(Direct Sequence Spread Spectrum) physical layer at 2.4GHz ISM band is adopted in the hardware prototype. To meet the high-speed requirement of physical layer, we have designed the MAC protocol layer with embedded firmware and FPGA. The prototype board is shown to be able to support the physical layer of 5GHz and 600Hz wireless LAN systems.

• Journal of IKEEE
• /
• v.2 no.2 s.3
• /
• pp.225-232
• /
• 1998

Currently NTSC, PAL, and SECOM are widely used for TV broadcasting systems. In Korea, NTSC has been used to reduce transmission bandwidth and broadband flickers using the Interlaced scanning method. Image data in the Interlaced scanning method require De-interlacing compensation for PC-based multimedia applications. The existing compensation algorithms such as ZOI, FOI, and ELA provieds simple computations and effective image compensation while the PSNR is low and horizontal and vertical edges are hardly detected. In this paper, the ADI(Adaptive De-Interlacing) algorithm that can increase PSNR and detect horizontal and vertical edges is proposed and a hardware system is implemented using three ACTEL 1020B FPGA chips. The system consists of the algorithm part implemented using two FPGAs and the memory control part implemented using rest one. Also the system operation is investigated for real time processing.

• Journal of Institute of Control, Robotics and Systems
• /
• v.5 no.6
• /
• pp.691-697
• /
• 1999

This paper describes the implementation of a high speed image processing board. This image processing board is consist of a image acquisition part and a image processing part. The image acquistion part is digitizing the image input data from CIS and save it to the dual port RAM. By putting on the dual port memory between two parts, during acquistion of image, the image processing part can be effectively processing of large-volume image data. Most of all image preprocessing part are integrated in a large-scaled FPGA. We arwe using ADSP-2181 of the Analog Device Inc., LTD. for a image processing part, and using the available all memory of DSP for the large-volume image data. Especially, using of IDMA exchanges the data with the external microprocessor or the external PC, and can watch the result of image processing and acquired image. Finally, we show that an implemented image processing board used for the simulation of image retreval by the one of the typical application.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.5
• /
• pp.36-43
• /
• 1999

A new design of a Direct Digital Frequency Synthesizer(DDFS) is presented, where a pipelined Coordinate Rotate Digital Computer(CORDIC) circuit is employed to calculate amplitude values of all the phase angles of sinusoidal waveforms produced. a near-optimal number of pipeline stages is determined based on an error analysis of calculated amplitude values in terms of the number of bits. The DDFS was implemented using a field programmable gate array, yielding a stable operating frequency of 11.75MHz. The measurement results show higher resolution, faster operating speed and simpler fabrication process, compared to ROM-based counterparts. The CORDIC-based DDFS yields 5 times higher resolution than conventional ROM-based versions.

• Journal of Sensor Science and Technology
• /
• v.29 no.1
• /
• pp.68-73
• /
• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• Proceedings of the KIEE Conference
• /
• 2007.04a
• /
• pp.289-291
• /
• 2007

The Digital Multimedia Broadcasting(DMB) system is developed to offer high quality audio-visual multimedia contents to the uses by the various portable terminals in the mobile environment. Integrated complex reception platform is required to receive multimedia broadcasting services transmitted from various transmission media. In this paper, we present the design and implementation technic for providing the both of terrestrial and satellite DMB services simultaneously using the same hardware platform. The implemented complex receiving terminal to accommodate these DMB services simultaneously need composed of it RF module. it baseband module, it complex control module and the complex de-multiplexer module. The complex control module is designed using uClinux operating system. The complex de-multiplexer, which perform the functions of the address decoder and each DMB stream de-multiplexer, is implemented. with FPGA device. The implemented platform is tested in a real environment and its performance is satisfied with required performance criteria.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 2008.04a
• /
• pp.251-254
• /
• 2008

유비쿼터스 네트워크의 실현을 위한 4세대 통신방식의 유력한 후보로 부상하는 OFDM (Orthogonal Frequency Division Multiplexing) 통신방식이 육상에 주목받고 있으며, 고속 데이터 전송을 위한 무선랜의 표준기술로 확정되어 있다. 해상 통신의 경우에서도 OFDM 통신방식은 단파대역을 이용한 데이터 전송방식으로 제안되고 있으며, ITU (International Telecommunication Union)는 해상통신에서 32-point FFT를 사용하도록 권고하고 있다. 해상 통신에서는 해양사고 및 조난 시에도 통신이 이루어져야 하는 한계상황을 고려하면, OFDM 통신방식의 중요 디바이스인 FFT는 저전력으로 동작되어야 한다. 따라서 본 논문에서는 OFDM 방식의 중요 디바이스인 32-point FFT를 저전력으로 동작시키기 위해 radix-2와 radix-4를 이용하여 저전력 32-point FFT 알고리즘을 제안한다. 최적화된 설계로 32-point FFT를 저전력 동작이 가능하도록 설계하였으며, 제안한 알고리즘은 VHDL로 구현하고 FPGA Spartan3 board에 장착하여 Matlab의 이론값과 비교, 검증하였다. 제안된 32-point FFT는 해상통신에서의 OFDM 적용을 위한 선도기술로 유용할 것이다.

• Journal of Sensor Science and Technology
• /
• v.27 no.1
• /
• pp.59-63
• /
• 2018

Among Internet of things (IoT) applications, the most demanding requirements for the widespread realization of many IoT visions are security and low power. In terms of security, IoT applications include tasks that are rarely addressed before such as secure computation, trusted sensing, and communication, privacy, and so on. These tasks ask for new and better techniques for the protection of data, software, and hardware. An integral part of hardware cryptographic primitives are secret keys and unique IDs. Physical Unclonable Functions(PUF) are a unique class of circuits that leverage the inherent variations in manufacturing process to create unique, unclonable IDs and secret keys. In this paper, we propose a low power Arbiter PUF circuit with low error rate and high reliability compared with conventional arbiter PUFs. The proposed PUF utilizes a power gating structure to save the power consumption in sleep mode, and uses a razor flip-flop to increase reliability. PUF has been designed and implemented using a FPGA and a ASIC chip (a 0.35 um technology). Experimental results show that our proposed PUF solves the metastability problem and reduce the power consumption of PUF compared to the conventional Arbiter PUF. It is expected that the proposed PUF can be used in systems required low power consumption and high reliability such as low power encryption processors and low power biomedical systems.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.6
• /
• pp.1533-1545
• /
• 1996

In this paper, the design and implementation of echo canceller with new variable step size algorithm is discussed. The method used in the new algorithm is to periodically adopt the test function which helps an optimal coefficient tracking. This algorithm outperforms LMS and VS algorithms in convergence speed and steady state error. As the period of test function is decreased, the speed of convergence is improved, but the number of calculation is increased, then the trade off between these parameters must be considered. Simulation results show new algorithm outperforms LMS and VS algorithms in convergence rate. For the design of hardware, circuit is designed with VHDL, and synthesized with Act1 withc is a FPGA library of ActelTM in use of synovation of InterGraph$^{TM}$. Verification of the synthesized circuit is carried out with simulator DLAB. The circuit based on the algorithm which is suggested in this paper calculated 7 radix places of inary number. A simulation data for the verification is based on the data of algorithm simulation. When the same input data is applied to the both simulation, output results of circuit simulation had slight difference in compare with that of algorithm simulation. The number of used gate is about 5,500 and We have 5.53MHz in maximum frequency.y.