• Journal of Korea Water Resources Association
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• v.38 no.10 s.159
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• pp.851-859
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• 2005

Normalized cross-correlation (correlation coefficient) is a useful measure for pattern matching in PIV (Particle Image Velocimetry) analysis. Because it does not have a corresponding simple expression in frequency domain, several fast but inexact measures have been used. Among them, three measures of correlation for PIV analysis and the normalized cross-correlation were evaluated with a sample calculation. The test revealed that all other proposed correlation measures sometimes show inaccurate results, except the normalized cross-correlation. However, correlation coefficient method has a weakpoint that it requires so long time for calculation. To overcome this shortcoming, a fast and exact method for calculating normalized cross-correlation is suggested. It adopts Fast Fourier Transform (FFT) for calculation of covariance and the successive-summing method for the denominator of correlation coefficient. The new algorithm showed that it is really fast and exact in calculating correlation coefficient.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.179-183
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• 2007

This paper is to implement a low power frequency Shift Keying(FSK) receiver using Xilinx System Generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital designs for better efficiency and reliability. The receiver functions on one bit data processing and supports data rates 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT, multiplication of twiddle factor is substituted by rotators. The design and simulation of the receiver is carried out in Simulink, then the simulink model is translated to a hardware model to implement FPGA using Xilinx System Generator and to verify performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.8
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• pp.1488-1494
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• 2008

This paper is to design and implement a low power noncoherent BFSK receiver intended for future deep space communication using Xilinx System generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital design for better efficiency and reliability. The receiver functions on one bit data processing and supports main data rate 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT and multiplication of twiddle factor for low power is substituted by rotators. The design and simulation of the receiver is carried out in Simulink then the Simulink model is translated to the hardware model to implement FPGA using Xilinx System Generator and to verify performance.

• Journal of Broadcast Engineering
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• v.8 no.3
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• pp.278-287
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• 2003

Noise in an image degrades image quality and deteriorates coding efficiency. Recently, various edge-preserving noise filtering methods based on the nonstationary image model have been proposed to overcome this problem. In most conventional nonstationary image models, however, pixels are assumed to be uncorrelated to each other in order not to Increase the computational burden too much. As a result, some detailed information is lost in the filtered results. In this paper, we propose a computationally feasible adaptive noise smoothing algorithm which considers the nonstationary correlation characteristics of images. We assume that an image has a nonstationary mean and can be segmented into subimages which have individually different stationary correlations. Taking advantage of the special structure of the covariance matrix that results from the proposed image model, we derive a computationally efficient FFT-based adaptive linear minimum mean-square-error filter. Justification for the proposed image model is presented and effectiveness of the proposed algorithm is demonstrated experimentally.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.253-256
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• 2009

This paper describes a core generator (FFT_Core_Gen) which generates Verilog HDL models of 8 different FFT/IFFT cores with $N=64{\times}2^k$($0{\leq}k{\leq}7$ for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture, and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage, and the internal data and twiddle factor has 14 bits. The generated FFT/IFFT cores have the SQNR of 58-dB for N=8,192 and 63-dB for N=64. The cores synthesized with a $0.35-{\mu}m$ CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed in $762.7-{\mu}s$, thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.368-376
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• 2006

This paper describes a Fcore_GenSim(Parameterized FFT Core Generation & Simulation Program), which can be used as an essential If(Intellectual Property) in various OFDM modem designs. The Fcore_Gensim is composed of two parts, a parameterized core generator(PFFT_CoreGen) that generates Verilog-HDL models of FFT cores, and a fixed-point FFT simulator(FXP_FFTSim) which can be used to estimate the SQNR performance of the generated cores. The parameters that can be specified for core generation are FFT length in the range of 64 ~2048-point and word-lengths of input/output/internal/twiddle data in the range of 8-b "24-b with 2-b step. Total 43,659 FFT cores can be generated by Fcore_Gensim. In addition, CBFP(Convergent Block Floating Point) scaling can be optionally specified. To achieve an optimized hardware and SQNR performance of the generated core, a hybrid structure of R2SDF and R2SDC stages and a hybrid algorithm of radix-2, radix-2/4, radix-2/4/8 are adopted according to FFT length and CBFP scaling.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.133-139
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• 2001

The economical detection of dual-tone multi-frequency(DTMF) signals is an important factor when developing cost-effective telecommunication equipment. Each channel has independently a DTMF receiver, and it informs the detected signal to processors. In order to detect the DTMF signals, this paper analyze the power spectra of the DTMF receiver by using the QFT algorithm. As experimental result, by analyzing 2$\^$M/ real data in terms of ITU-T specification, it show that the QFT algorithm improve the performance of the DTMF receiver and can save memory waste and can the real-time processing.

• The Journal of the Acoustical Society of Korea
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• v.28 no.7
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• pp.653-660
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• 2009

This paper proposes a robust audio watermarking algorithm for copyright protection and improvement of sound quality after embedding a watermark into an original sound. The proposed method computes the FFT (fast Fourier transform) of the original sound signal and divides the spectrum into a subbands. Then, it is necessary to calculate the energy of each subband and sort n subbands in descending order corresponding to its power. After calculating the energy we choose k subbands in sorted order and find p peaks in each selected subbands, and then embed a length m watermark around the p peaks. When the listeners hear the watermarked sound, they do not recognize any distortions. Furthermore, the proposed method is robust as much as Cox's method to MP3 compression, cropping, FFT echo attacks. In addition to this, the experimental results show that the proposed method is generally 10 dB higher than Cox's method in SNR (signal-to-noise ratio) aspect.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.503-506
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• 1998

본 연구에서는 방대한 양의 데이터를 실시간으로 처리하기 위한 병렬 고속 디지털 신호처리시스템을 제안한다. 시스템의 성능을 평가할 수 있는 확률적인 분석방법을 제시하며, FFT 와 같이 보드간 또는 프로세서간 통신부담이 많은 알고리즘과 행렬연산과 같이 통신부담이 적은 알고리즘에 적용하여 본다. 제안한 시스템의 다양한 구성에 대하여 두 가지 알고리듬의 성능을 확률적 방법으로 평가하였으며, 그 결과는 알고리즘 분석에 듸한 성능수치와 근접함을 확인하였다. FFT는 프로세서 개수가 증가해도 보드수가 많아지면 성능이 감소하였으며, 행렬연산은 프로세서 개수에 비례하여 시스템의 성능이 선형적으로 증가함을 확인하였다.