• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.1
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• pp.21-26
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• 2003

4H-SiC Schottky rectifiers were exposed to pure Ar discharges in a planar coil Inductively Coupled Plasma system, as a function of source power, of chuck power and process pressure. The reverse breakdown voltage ($V_B$) decreased as a result of plasma exposure due to the creation of surface defects associated with the ion bombardment. The magnitude of the decrease was a function of both ion flux and ion energy. The forward turn-on voltage ($V_F$), on-state resistance ($R_{ON}$) and diode ideality factor (n) all increased after plasma exposure. The changes in all of the rectifier parameters were minimized at low power, high pressure plasma conditions.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.208-211
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• 1997

We have fabricated a single-electron-tunneling(SET) transistor with a dual gate geometry based on the SOI structure prepared by SIMOX wafers. The split-gate is the lower-gate is the lower-level gate and located ∼ 100${\AA}$ right above the inversion layer 2DEG active channel, which yields strong carrier confinement with fully controllable tunneling potential barrier. The transistor is operating at low temperatures and exhibits the single electron tunneling behavior through nano-size quantum dot. The Coulomb-Blockade oscillation is demonstrated at 15mK and its periodicity of 16.4mV in the upper-gate voltage corresponds to the formation of quantum dots with a capacity of 9.7aF. For non-linear transport regime, Coulomb-staircases are clearly observed up to four current steps in the range of 100mV drain-source bias. The I-V characteristics near the zero-bias displays typical Coulomb-gap due to one-electron charging effect.

• The Journal of Engineering Geology
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• v.17 no.1 s.50
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• pp.1-13
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• 2007

In order to evaluate the local site effects at two town fortress areas in Korea where stone parapets were col-lapsed by historical earthquakes, site characteristics were assessed using site investigations such as borehole drillings and seismic tests. Equivalent-linear site response analyses were conducted based on the shear ways velocity ($V_s$) profiles and geotechnical characteristics determined from site investigations. The study sites are categorized as site classes C and B according to the mean $V_s$ to 30 m ranging from 500 to 850 m/s, and their site periods are distributed in the short period range of 0.06 to 0.16 sec, which contains the natural period of fortress wall and stone parapet. From the results of site response analyses in the study areas, for site class C indicating most of site conditions, contrary to site class B, the short-period (0.1-0.5 sec) and mid-period (0.4-2.0 sec) site coefficients, $F_a$ and $F_v$ specified in the Korean seismic design guide, underestimate the ground motion in short-period band and overestimate the ground motion in mid-period band, respectively, due to the high amplification in short period range, which represent the site-specific seismic response characteristics. These site-specific response characteristics indicate the potential of resonance in fortress walls during earthquake and furthermore could strongly affect the collapse of parapets resulted from seismic events in historical records.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.305-310
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• 2008

Deep trench etching of silicon was investigated as a function of RF source power, DC bias voltage, $C_4F_8$ gas flow rate, and $O_2$ gas addition. On increasing the RF source power from 300 W to 700 W, the etch rate was increased from $3.52{\mu}m/min$ to $7.07{\mu}m/min$. The addition of $O_2$ gas improved the etch rate and the selectivity. The highest etch rate is achieved at the $O_2$ gas addition of 12 %, The selectivity to PR was 65.75 with $O_2$ gas addition of 24 %. At DC bias voltage of -40 V and $C_4F_8$ gas flow rate of 30 seem, We were able to achieve etch rate as high as $5.25{\mu}m/min$ with good etch profile.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.5
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• pp.536-541
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• 2003

In order to avoid oxygen contamination on the diamond surface as far as possible during the device process, the A1/Ca $F_2$/diamond MISFET(metal-insulator-semiconductor field-effect transistor) was prepared by ultrahigh vacuum process and its electrical properties were investigated. The surface conductive layer of fluorinated diamond surface was employed for the conducting channel of the MISFET. The observed effective mobility(${\mu}$e$\_$ff/) of the MISFET was 300 c $m^2$/Vs, which is the highest value obtained until now in the diamond FET. Besides, the measured surface state density of the device was ∼10$\^$11//c $m^2$ eV, which is comparable with conventional Si MOSFET$\_$s/(metal-oxide-semiconductor field-effect-transistors). This work is the first report of the fluorinated diamond MISFET prepared by ultrahigh vacuum process and its application to inverter circuit.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.95-98
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• 2003

The positive column discharge characteristics in the long gap (440 ${\mu}m$) are investigated based on the voltage distribution among three electrodes. In particular, the effects of the amplitude and width of the short pulse applied to the address electrode on the positive column discharge characteristics are examined intensively. By proper controlling of the amplitude and width of the address short pulse, it is found that the positive column discharge in the long gap is well constructed. As a result, under the stable static voltage margin condition, the firing and sustaining voltages are as low as those of conventional short gap(60 ${\mu}m$) discharge($V _f=220V$, $V_s=150V$) and the color purity is improved. Moreover, the luminous efficiency increases up to 60% in comparison with the conventional case.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• Electrical & Electronic Materials
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• v.6 no.3
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• pp.269-275
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• 1993

미래의 ULSI 소자의 게이트 산화막으로 이용하기 위하여 $N_{2}$O 가스 분위기에서 기존의 전기로를 이용한 실리콘의 열산화에 의해 $N_{2}$O 산화막을 형성하였고 MOS 소자를 제작하여 전기적 특성을 고찰하였다. 900.deg.C에서 90분간 산화한 $N_{2}$O 산화막의 경우, 플랫밴드 전압( $V_{FB}$ ), 고정전하밀도 ( $N_{f}$)와 플랫밴드 전압의 변화량(.DELTA. $V_{FB}$ )은 각각 0.81[V], 6.7x$10^{10}$[$cm^{-2}$]와 80~95[mV]를 나타내었다. $N_{2}$O 산화막의 전기전도기구는 저전계 영역에서는 Fowler-Nordheim 터널링, 고전계영역에서는 Poole-Frenkel 방출이 지배적으로 나타났고 절연파괴전계는 16[MV/cm]로 높게 나타났다. 따라서 $N_{2}$O 산화로 형성된 게이트 산화막이 ULSI소자의 게이트 유전체로 응용이 가능하리라 생각된다..

• Journal of the Korean Wood Science and Technology
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• v.12 no.3
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• pp.3-8
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• 1984

It is shown that Paul and Jones' Rule of Mixtures modified by Smith and Cox's theory can be used for the fiber-reinforced, sulfur-based composites, when the constant for the linear regression equation is given. The computation results, programmed by Hewlett Packard 75C (HP 75C) using math rom pack for the linear regression form, expressed as $E_c=\frac{1}{3}aE_fV_f+bE_mV_m$, turn out to be a=3.27-3.54 b=-2.47~-2.80. This results indicate that the factors such as density of fiber mat and the amount of matrix used have nothing for affecting the numerical value of the constants a and b of the linear regression form. Conclusively this results also show that the Paul and Jones' Rule of Mixtures which has been used for the composites made by randomly-oriented long fiber can also be used for the composites made by short fiber with the same fiber orientation such as wood and lignocellulosic fibers.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.39-46
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• 2013

In this paper, organic solar cells(OSCs) based on bulk-heterojunction structures were fabricated by spin coating method using polymer P3HT and fullerene PCBM as a photoactive layer. The fabricated OSCs had a simple glass/ITO/PEDOT:PSS/P3HT:PCBM/Al structures. The photoactive layer of mixed P3HT:PCBM was formed with 1:1 weight ratio. The hole transport layer(HTL) was used conducting polymer PEDOT:PSS concentration with gold nanoparticles. The annealing temperature and concentration of nanoparticles in HTL were verified to improve the OSC characterization. The percentage of gold nanoparticles in HTL were 0.5 wt% and 1.0 wt%, and the surface morphology, electrical properties and absorption intensities were investigated. The devices were 0.5 wt%, and the highest 3.1% of the powder conversion efficiency(PCE), 10.2 $mA/cm^2$ of the maximum short circuit current density($J_{SC}$), 0.535V of the open circuit voltage($V_{OC}$) and 55.8% of the fill factor(F.F) could be obtained when the nanoparticle concertration was 0.5 wt%. The annealing temperature of HTL was $110^{\circ}C$, $130^{\circ}C$, $150^{\circ}C$ in vacuum oven and measured the absorption intensities, surface morphology, crystallinity and electrical properties were investigated. The best property was obtained in HTL annealed at $130^{\circ}C$ for gold nanoparticles of 0.5 wt%, showing that $J_{SC}$, $V_{OC}$, F.F and PCE were about 12.0 $mA/cm^2$, 0.525V, 64.2% and 4.0%, respectively.