• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.249-251
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• 2003

This paper discribes the analysis of the breakdown voltage characteristics of SOI LIGBT with dual epi-layer. In case of SOI LIGBT with dual epi-layer, if we used high doping concentration in epi-layer, we obtained higher breakdown voltage compared with typical device because of charge compensation effect, and we obtained low on-state resistivity characteristic in the same breakdown voltage. In this paper, we analyzed on-state and off-state characteristics of SOI LIGBT with dual epi-layer. Breakdown voltage of proposed LIGBT was shown 125V when $T_1=T_2=2.5{\mu}m$, $N_1=7{\times}10^{15}/cm^3$ and $N_2=3{\times}10^{15}/cm^3$, respectively Although we used high doping concentration and thin epi-layer thickness, breakdown voltage was increased compared with conventional devices.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.8
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• pp.38-43
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• 1998

An analytical model for the surface field distribution of the RESURF (reduced surface field)LD(lateral double-diffused) MOS is presented in terms of the doping concentration, the thickness of the n epi layer, the p substrate concentration, and the epi layer length. The reuslts are used to determine the breakdown voltage due to the surface field as a function of the epi layer length. The maximum breakdown voltage of the device is found to be that of the vertical n$^{+}$n$^{[-10]}$ p$^{[-10]}$ junction. Analytical results of the breakdown voltage vs. the epi layer length agree well with the numerical simulation results using MEDICI.I.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.101-102
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• 2005

SiC lateral power semiconductor device has high breakdown voltage and low on-state voltage drop due to the material characteristics. And, because the high breakdown voltage can be obtained, RESURF technique is mostly used in silicon power semiconductor devices. In this paper, we presents the electrical characteristics of the 4H-SiC RESURF LDMOSFET as a function of the epi-layer length, concentration and thickness. 240~780V of breakdown voltage can be obtained as a function of epi-layer length and thickness with same epi-layer concentration.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.813-817
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• 2006

In this paper, we analyzed the breakdown voltage and on-resistance of the multi-RESURF SOI LDMOSFET as a function of epi-layer concentration. P-/n-epi layer thickness and doping concentration of the proposed structure are varied from $2{\sim}5{\mu}m\;and\;1\{times}10^{15}/cm^{3}^{\sim}9\{times}10^{15}/cm^{3}$ to find optimum breakdown voltage and on-resistance of the proposed structure. The maximum breakdown voltage of the proposed structure is $224\;V\;at\;R_{on}=0.2{\Omega}-mon^{2}\;with\;P_{epi}=3\{times}10^{15}/cm^{3},\;N_{epi}=7\{times}10^{15}/cm^{3}\;and\;L_{epi}=10{\mu}m$. Characteristics of the device are verified by two-dimensional process simulator ATHENA and device simulator ATLAS.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.274-283
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• 2014

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.3
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• pp.161-164
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• 2000

A simple methode for calculating the forward voltage drop of IGBTs is presented, on the voltage drops on the p+ body, the reverse biased depletion region between p+body and epi-layer, the epi layer, and the forward biased collector junction. The decrease of the total current density in the epi layer near the p+ body is taken into account. The proposed methode allows a simple but accurate determination of the forward voltage drop in IGBTs, avoiding the complex path taken in the previous model for the forward voltage drops on channel, accumulation region, and epi region. Numerical simulations for 1kV NPT-IGBT with a uniformly doped collector are shown to support the analytical results.

• Korean Journal of Materials Research
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• v.24 no.12
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• pp.682-688
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• 2014

Physical and chemical changes in a polished wafer and in $2.5{\mu}m$ & $4{\mu}m$ epitaxially grown Si layer wafers (Epilayer wafer) after surface treatment were investigated. We characterized the influence of surface treatment on wafer properties such as surface roughness and the chemical composition and bonds. After each surface treatment, the physical change of the wafer surface was evaluated by atomic force microscopy to confirm the surface morphology and roughness. In addition, chemical changes in the wafer surface were studied by X-ray photoemission spectroscopy measurement. Changes in the chemical composition were confirmed before and after the surface treatment. By combined analysis of the physical and chemical changes, we found that diluted hydrofluoric acid treatment is more effective than buffered oxide etching for $SiO_2$ removal in both polished and Epi-Layer wafers; however, the etch rate and the surface roughness in the given treatment are different among the polished $2.5{\mu}m$ and $4{\mu}m$ Epi-layer wafers in spite of the identical bulk structural properties of these wafers. This study therefore suggests that independent surface treatment optimization is required for each wafer type, $2.5{\mu}m$ and $4{\mu}m$, due to the meaningful differences in the initial surface chemical and physical properties.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.350-350
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• 2010

Silicon carbide (SiC), one of the well known wide band gap semiconductors, shows high thermal conductivities, chemical inertness and breakdown energies. The design of normally-off 4H-SiC VJFETs [1] has been reported and 4H-SiC VJFETs with different lateral JFET channel opening dimensions have been studied [2]. In this work, 4H-SiC based VJFETs has been designed using the device simulator (ATLAS, Silvaco Data System, Inc). We varied the n-epi layer thickness (from $6\;{\mu}m$ to $10\;{\mu}m$) and the channel width (from $0.9\;{\mu}m$ to $1.2\;{\mu}m$), and investigated the static characteristics as blocking voltages, threshold voltages, on-resistances. We have shown that silicon carbide JFET structures of highly intensified blocking voltages with optimized figures of merit can thus be achieved by adjusting the epi layer thickness and channel width.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.25 no.2
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• pp.56-61
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• 2015

The effects of the growth temperature on the properties of a-plane GaN epi-layer on r-plane sapphire by HVPE were studied, when the constant V/III ratio and the flow rate of HCl for the Ga source channel was fixed at 10 and 700 sccm, respectively. Additionally the effects of V/III ratios for source gasses were studied when growth temperature and the flow rate of HCl for the Ga source channel was fixed at $1000^{\circ}C$ and 700 sccm, respectively. As the growth temperature was increased, the values of Full Width Half Maximum (FWHM) for Rocking curve (RC) of a-plane GaN (11-20) epi-layer were decreased and thickness of a-plane GaN epi-layer were increased. As V/III ratios were increased at $1000^{\circ}C$, the values of FWHM for RC of a-plane GaN (11-20) were declined and thickness of a-plane GaN epi-layer were increased. The a-plane GaN (11-20) epi-layer grown at $1000^{\circ}C$ and V/III ratio = 10 showed the lowest value FWHM for RC of a-plane GaN (11-20) for 734 arcsec and the smallest dependence of Azimuth angle for FWHM of (11-20) RCs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.3
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• pp.22-27
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• 1976

For linear IC design, one has to know the epi thickness, resistivity, and structure of buried island inserted between epi and substrate because the mask structure can only be changed for linear IC consisted of various type of transistors to be made for desired specific function. The interrelation of IC operational and saturation voltages with epi resistivity, theckness and divice structure are studied and presented in graphic forms so that IC design engineers can utilize them.