• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.6
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• pp.63-70
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• 2011

A bicycle is different from vehicles in the structure that a rider is fully exposed to the surrounding environment. Therefore, it needs to make use of prior information about local weather, air quality, trail road condition. Moreover, since it depends on human power for moving, it should acquire route property such as hill slope, winding, and road surface to improve its efficiency in everyday use. Recent mobile applications which are to be used during bicycle riding let us aware of the necessity of development of intelligent bicycles. This study aims to develop a riding state (up-hill, down-hill, accelerating, braking) recognition algorithm using a low-power wrist watch type embedded system which has 3-axis accelerometer and wireless communication capability. The developed algorithm was applied to 19 experimental riding data and showed more than 95% of correct recognition over 83.3% of the total dataset. The altitude and temperature sensor also in the embedded system mounted on the bicycle is being used to improve the accuracy of the algorithm. The developed riding state recognition algorithm is expected to be a platform technology for intelligent bicycle interface system.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.83-93
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• 2013

Recently, the SURF algorithm, which is conjugated for object tracking system as part of many computer vision applications, is a well-known scale- and rotation-invariant feature detection algorithm. The SURF, due to its high computational complexity, there is essential to develop a hardware accelerator in order to be used on an IP in embedded environment. However, the SURF requires a huge local memory, causing many problems that increase the chip size and decrease the value of IP in ASIC and SoC system design. In this paper, we proposed a way to design a SURF algorithm in hardware with greatly reduced local memory by partitioning the algorithms into several Sub-IPs using external memory and a DMA. To justify validity of the proposed method, we developed an example of simplified object tracking algorithm. The execution speed of the hardware IP was about 31 frame/sec, the logic size was about 74Kgate in the 30nm technology with 81Kbytes local memory in the embedded system platform consisting of ARM Cortex-M0 processor, AMBA bus(AHB-lite and APB), DMA and a SDRAM controller. Hence, it can be used to the hardware IP of SoC Chip. If the image processing algorithm akin to SURF is applied to the method proposed in this paper, it is expected that it can implement an efficient hardware design for target application.

• Journal of the Korea institute for structural maintenance and inspection
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• v.27 no.4
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• pp.33-44
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• 2023

Wind power is one of the most efficient and reliable energy sources in the transition to a low-carbon society. In particular, offshore wind power provides a high-quality and stable wind resource compared to onshore wind power while both present a higher installed capacity than other renewables. In this paper, we present our new program, the X-WIND program well suitable for the assessment of the substructure of offshore wind turbines. We have developed this program to increase the usability of analysis programs for offshore wind energy substructures by addressing the shortcomings of existing programs. Unlike the existing programs which cannot solely perform the substructure analyses or lack pre-post processors, our X-WIND program can complete the assessment analysis for the offshore wind turbines alone. The X-WIND program is embedded in AutoCAD so that both design and analysis are performed on a single platform. This also performs static and dynamic analysis for wind, wave, and current loads, essential for offshore wind power structures, and includes pre/post processors for designs, mesh developments, graph plotting, and code checking. With this expertise, our program enhances the usability of analysis programs for offshore wind energy substructures, promoting convenience and efficiency.

• Science of Emotion and Sensibility
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• v.14 no.2
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• pp.221-226
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• 2011

Although diverse researches on sensing method of human movement have been performed, there are still many limitations to the existing methods. As a part of supplementing the limitations to the existing motion sensing methods, this study aimed to execute an exploratory examination on a POF-based sleeve-shaped motion sensor for less restrictive sensing of human movement. In this study, a set of POF-based motion sensor, which was embedded in a sleeve-shaped platform was devised, and a set of exploratory experiments was performed on the possibility of sensing of human movement as diverse as in daily life, through this device. The scope of this research was limited to an exploration on the possibility and basic elements of POF-based sleeve-shaped motion sensor, while the influence of sleeve patterns, those of wearer's somatotype, those of sewing method were not studied in this study. When compared to the pre-existing methods, the POF-based motion sensor platformed on sleeve in this study, which was purposively devised to be applied to the motion sensing clothing shows some beneficial characteristics : more sensitive measurement on human motion, low cost, no timely restriction in sensing, no request for gigantic apparatus and space for sensing.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.485-496
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• 2008

As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12A
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• pp.925-932
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• 2009

Precise temperature monitoring is the major preconditioning to supervise quality losses within the transport chain for fresh products. ISO/IEC18000-6REV1 defines new protocols supporting BAP(Battery Assisted Passive) RFID tag which is completely compatible with EPCglobal Class1 Generation2 specification. In this paper, we designed a modem supporting BAP RFID tag with FPGA(Field Programmable Gate Array) and implemented sensor data processing function defined in ISO/IEC18000-6REV1. The transmit block of the modem supports pulse shaping filter and the output signal of the implemented RFID reader is satisfied with the spectrum mask defined in the standard. The receive block of the modem uses Gardner TED to synchronize timing of symbol. In this paper, we designed a modem supporting ISO/IEC18000-6REV1 standard and developed a RFID reader sndard. The developed RFID reader sndard can recognize sensor tag and passive tag in the wireless environment and supports real-time processing of the sensor data in the embedded linux platform.

• The KIPS Transactions:PartC
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• v.10C no.5
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• pp.585-594
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• 2003

Java card is one of promising smart card platform with java technology. Java card defines necessary packages and classes for Embedded device that have small memory such as smart card Jana card is compatible with EMV that is Industry specification standard and ISO-7816 that is international standard. However, Java card is not offers user authentication protocol. In this paper, We design and implement an user authentication protocol applicable wireless devices based on Java Card using standard 3GPP Specification (SMS), Java Card Specification (APDU), Cryptography and so on. Our Java Card user authentication techniques can possibly be applied to the area of M-Commerce, Wireless Security, E-Payment System, Mobile Internet, Global Position Service, Ubiquitous Computing and so on.

• Journal of the Korean Society for Marine Environment & Energy
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• v.14 no.4
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• pp.280-286
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• 2011

In this research, the oil detection method and the characteristic of sensor using the selective reaction of silicone rubber in response to hydrocarbon oil will be described. As a sensing principle, the swelling property of silicone rubber in response to hydrocarbon fuel is used, also a strain gauge is used to transduce the volume change to an electrical signal. The sensor core is manufactured with a strain gauge embedded in silicone rubber by the curing process and experiments for characteristics of sensor core with various oils were carried out. It is shown that the sensor core can be used as an oil spill detection sensor. Also, for the application to the sea area, a buoy type sensor platform is integrated with a sensor core and a strain amplifier and it is tested in the simulated oil spill condition. In this study, it is proven that the integrated sensor can be used for the detection of various oils.

• Smart Media Journal
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• v.1 no.1
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• pp.1-9
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• 2012

This Paper proposes an effective SoC hardware architecture implementing a VDP for Full HD TVs. The proposed architecture makes real time video processing possible with supporting efficient bus architecture and flexible interface. Video IP cores in the VDP are designed to provide a high quality of improved image enhancement function. The Avalon interface is adopted to guarantee real-time capability to IPs as well as SoC integration. This leads to reduced design time and also enhanced designer's convenience due to the easiness in IP addition, deletion, and revision for IP verification and SoC integration. The embedded software makes it possible to implement flexible real-time system by controlling setting parameter details and data transmitting schemes in real-time. The proposed VDP SoC design is implemented on Cyclon III SoPC platform. The experimental results show that our proposed architecture of the VDP SoC successfully provides required quality of Video image by converting SD level input to Full HD level image.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.11
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• pp.2113-2120
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• 2015

This paper presents an integrated receiver to support multimode broadcasting standards such as DVB-T2, DVB-C2, and DVB-S2 in a single platform. The integrated receiver consists of a tuner block, a receiver engine, a frame processor, and an A/V decoder. The receiver engine includes a channel decoding engine and a demodulation engine to perform OFDM and APSK demodulations. The frame processor performs deinterleaving and BB frame decoding functions. The demodulator engine and the frame processor are implemented in two FPGA devices and DSP-based embedded software, respectively. To verify the functionality of the integrated receiver, it is tested in the laboratory. Commercial PC-based modulators are used to generate the DVB-T2, DVB-C2, and DVB-S2 modulated signals. The integrated receiver was tested under various operation modes as specified in the standards such as DVB-T2, DVB-C2, and DVB-S2 and showed successful operation in all the scenarios tested.