• The Journal of the Korea institute of electronic communication sciences
• /
• v.5 no.1
• /
• pp.17-22
• /
• 2010

Generally, there are Chua's Circuit, Lorenz Circuit and Duffing circuit in the chaos circuit. Among these chaos circuits, Chua's circuit is well known to make the electronic parts easily. Chua's circuit is the constitute of the linearelements. These are constitute of Resistor component(R), inductor component(L), capacitor(C), and nonlinear element which is constitute of nonlinear resistor. However, L element have a difficult problem to implement real hardware by using commercial parts. Due to this, it has a saturation characteristic. In this paper, we analyzed the simplified Chua's circuit which is replace L to C by PSPICE program. Because L element has a difficult problem to make a real hardware, L has a saturation characteristic and we also confirm this analysis as the result.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.2
• /
• pp.875-880
• /
• 2018

This paper proposes a novel combined compensation structure in the infrared receiver chip. For the infrared communication chip, the current-voltage (I-V) convert circuit is crucial and important. The circuit is composed by the transimpedance amplifier (TIA) and the combined compensation structures. The TIA converts the incited photons into photocurrent. In order to amplify the photocurrent and avoid the saturation, the TIA uses the combined compensation circuit. This novel compensation structure has the low frequency compensation and high frequency compensation circuit. The low frequency compensation circuit rejects the low frequency photocurrent in the ambient light preventing the saturation. The high frequency compensation circuit raises the high frequency input impedance preserving the sensitivity to the signal of interest. This circuit was implemented in a $0.6{\mu}m$ BiCMOS process. Simulation of the proposed circuit is carried out in the Cadence software, with the 3V power supply, it achieves a low frequency photocurrent rejection and the gain keeps 109dB ranging from 10nA to $300{\mu}A$. The test result fits the simulation and all the results exploit the validity of the circuit.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.6
• /
• pp.732-741
• /
• 2018

In order to maximize the usable capacity of a BMS (battery management system) that uses several battery cells connected in series, a cell balancing technique that equips each cell with the same voltage is needed. In the active cell balancing circuit using a multi-winding transformer, a balancing circuit that transfers energy directly to the cell (cell-to-cell) is composed of a PMOS switch and a gate driving chip for driving the NMOS switch. The TLP2748 photocoupler and the TLP2745 photocoupler are required, resulting in increased cost and reduced integration. In this paper, instead of driving PMOS and NMOS switching devices by using photocoupler, we proposed 70V BCD process based PMOS gate driving circuit, NMOS gate driving circuit, PMOS gate driving circuit and NMOS gate driving circuit with improved switching time. ${\Delta}t$ of the PMOS gate drive switch with improved switching time was 8.9 ns and ${\Delta}t$ of the NMOS gate drive switch was 9.9 ns.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.385-388
• /
• 1999

A new frequency-variant equivalent circuit model of power/ground plane is presented. The equivalent circuit is modeled with grid cells. The circuit parameters of each cell were extracted by using Fasthenry. To verify the developed circuit model, its s-parameters are compared with the measured s-parameters 〔2〕 and the full-wave simulation-based s-parameters. Consequently, it is shown that our frequency-variant equivalent circuit model can accurately predict imperfect ground effects under the high frequency operation of electronic package.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.4
• /
• pp.443-450
• /
• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.12 no.3
• /
• pp.312-320
• /
• 2019

In this paper, we design a 512Kb eFlash IP using 110nm eFlash cells. We proposed eFlash core circuit such as row driver circuit (CG/SL driver circuit), write BL driver circuit (write BL switch circuit and PBL switch select circuit), read BL switch circuit, and read BL S/A circuit which satisfy eFlash cell program, erase and read operation. In addition, instead of using a cross-coupled NMOS transistor as a conventional unit charge pump circuit, we propose a circuit boosting the gate of the 12V NMOS precharging transistor whose body is GND, so that the precharging node of the VPP unit charge pump is normally precharged to the voltage of VIN and thus the pumping current is increased in the VPP (boosted voltage) voltage generator circuit supplying the VPP voltage of 9.5V in the program mode and that of 11.5V in the erase mode. A 12V native NMOS pumping capacitor with a bigger pumping current and a smaller layout area than a PMOS pumping capacitor was used as the pumping capacitor. On the other hand, the layout area of the 512Kb eFlash memory IP designed based on the 110nm eFlash process is $933.22{\mu}m{\times}925{\mu}m(=0.8632mm^2)$.

• 제어로봇시스템학회:학술대회논문집
• /
• 1996.10a
• /
• pp.255-258
• /
• 1996

This paper describes a DC voltage controller for the DC power supply which is constructed using the full-bridged MOS-FET DC-to-RF power inverter and rectifier. The full-bridged MOS-FET DC-to-RF inverter consisting of four MOSFET arrays and an output power transformer has a control function which is able to control the RF output power when the widths of the pulse voltages which are fed to four MOS-FET arrays of the fall-bridged inverter are changed using the pulse width control circuit. The power conversion efficiency of the full-bridged MOS-FET DC-to-RF power inverter was approximately 85 % when the duty cycles of the pulse voltages were changed from 30 % to 50 %. The RF output voltage from the full-bridged MOS-FET DC-to-RF inverter is fed to the rectifier circuit through the output transformer. The rectifier circuit consists of GaAs schottky diodes and filters, each of which is made of a coil and capacitors. The power conversion efficiency of the rectifier circuit was over 80 % when the duty cycles of the pulse voltages were changed from 30 % to 50 %. The output voltage of the rectifier circuit was changed from 34.7V to 37.6 V when the duty cycles of the pulse voltages were changed from 30 % to 50 %.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.22 no.6
• /
• pp.1-6
• /
• 2008

In this paper describes the process of designing a protection circuit against an open or short electronic ballast. An open electronic ballast creates high voltages in a regular period, which a lies voltage stress on switching devices. On the other hand, a shorted output generates excessive current, causing problems such as heat generation in the ballast and reduced lifespan of semiconductor devices. This study proposes a protection circuit consisting of TTL and passive devices to resolve the problems. The proposed protection circuit offers the benefits of low cost and high reliability. The proposed circuit was connected to an actual ballast to demonstrate its applicability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.9
• /
• pp.686-691
• /
• 2012

In this paper, we designed a Chua's chaotic circuit using transcondcutor based nonlinear resistor. Proposed chaotic circuit consist of L, C, R and transcondcutor based Chua's diode. We performed SPICE simulation for chaotic dynamics such as time seriesform, frequency analysis and phase plane of the circuit. Chaotic dynamics of the circuit was analysed according to MOS size variation of the operational transconductance amplifier. Also, we performed SPICE circuit analysis for temperature dependance of the circuit. SPICE results showed that chaotic dynamics of the circuit varied according to the temperature variation and chaotic signals were generated in specific temperature conditions.

• Proceedings of the KIEE Conference
• /
• 2002.04a
• /
• pp.183-185
• /
• 2002

This paper proposes the test method for the testing of a RLC parallel circuit on the electronic circuit board. This method utilizes a guarding circuit and a phase detection circuit. The guarding circuit separates electrically the tested device or circuit from printed circuit board. Phase detector estimates the phase difference from two signals, voltage and current. This method computes R. L and C value from phase difference($\theta$) and impedance value(Z) obtained by enforcing two other frequence stimulus under the guarding state.