• Journal of the Microelectronics and Packaging Society
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• v.30 no.1
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• pp.30-41
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• 2023

With the aggressive down-scaling of advanced integrated circuits (ICs), electronic packages have become the bottleneck of both reliability and performance of whole electronic systems. In order to resolve the reliability issues, Institute of Electrical and Electronics Engineers (IEEE) laid down a roadmap on fault detection and diagnosis (FDD), thrusting the digital twin: a combination of reliability physics and artificial intelligence (AI). In this paper, we especially review research works regarding the signal-based FDD approaches on the electronic packages. We also discuss the research trend of FDD utilizing AI techniques.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.51-69
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• 2001

Japan Jisso Technology Roadmap 2001 (JJTR2001) was published by JEITA in April 2001. Future electronic products request further higher assembly technology (ex. Finer pitch packages & components, 3D assembly, etc.) to reduce size and improve performance of the electric products. For LSI Packages, finer ball pitch technology and finer chip connection technology will be developed. For electric components, further size reduction will be developed. For Jisso (assembly) machine, finer pitch assembly and short tact time technology will be developed. Mr. Utsunomiya will present PCB roadmap next.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.55-62
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• 2019

Stiffness-gradient stretchable electronic packages of the soft PDMS/hard PDMS/FPCB structure were processed using the polydimethylsiloxane (PDMS) as the base substrate and the more stiff flexible printed circuit board (FPCB) as the island substrate. The elastic characteristics of the stretchable packages were estimated and their long-term reliabilities on stretching cycles and bending cycles were characterized. With 0.28 MPa, 1.74 MPa, and 1.85 GPa as the elastic moduli of the soft PDMS, hard PDMS, and FPCB, respectively, the effective elastic modulus of the soft PDMS/hard PDMS/FPCB package was estimated as 0.6 MPa. The resistance of the stretchable packages varied for 2.8~4.3% with stretching cycles ranging at 0~0.3 strain up to 15,000 cycles and for 0.9~1.5% with 15,000 bending cycles at a bending radius of 25 mm.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.1-4
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• 2015

Qualification includes all activities to demonstrate that a product meets and exceeds the reliability goals. Manufacturers need to spend time and resources for the qualification processes under the pressure of reducing time to market, as well as offering a competitive price. Failure to qualify a product could result in economic loss such as warranty and recall claims and the manufacturer could lose the reputation in the market. In order to provide valid and reliable qualification results, manufacturers are required to make extra effort based on the operational and environmental characteristics of the product. This paper discusses optimal interval censoring design for reliability prediction of electronic packages under limited time and resources. This design should provide more accurate assessment of package capability and thus deliver better reliability prediction.

• Proceedings of the KWS Conference
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• 2003.11a
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• pp.83-85
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• 2003

This paper is investigated the shear strength by using the micro shear-punch test method for Sn-37Pb alloy, binary and ternary alloys of environment-friendly Pb-free solder alloys which would be surely applicable to the electronic packages. As a result, in case of Max. shear strength, Sn-4Ag-0.5Cu has the highest value and Sn-37Pb has the lowest value on every condition of experiment temperature. Also, In case of Pb-free solder joint specimens, it was found that Pb-free solder alloys have higher value of shear strength than eutectic Sn-Pb solder alloy and Sn-4Ag-0.5Cu has the highest value.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.10
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• pp.183-190
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• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.15-15
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• 2004

• Corrosion Science and Technology
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• v.6 no.6
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• pp.282-285
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• 2007

Smaller size and higher integration of electronic systems make narrower interconnect pitch not only in chip-level but also in package-level. Moreover electronic systems are required to operate in harsher conditions, that is, higher current / voltage, elevated temperature / humidity, and complex chemical contaminants. Under these severe circumstances, electronic components respond to applied voltages by electrochemically ionization of metals and conducting filament forms between anode and cathode across a nonmetallic medium. This phenomenon is called as the electrochemical migration. Many kinds of metal (Cu, Ag, SnPb, Sn etc) using in electronic packages are failed by ECM. Eutectic SnPb which is used in various electronic packaging structures, that is, printed circuit boards, plastic-encapsulated packages, organic display panels, and tape chip carriers, chip-on-films etc. And the material for soldering (eutectic SnPb) using in electronic package easily makes insulation failure by ECM. In real PCB system, not only metals but also many chemical species are included. And these chemical species act as resources of contamination. Model test systems were developed to characterize the migration phenomena without contamination effect. The serpentine-shape pattern was developed for analyzing relationship of applied voltage bias and failure lifetime by the temperature / humidity biased(THB) test.

• Polymer Science and Technology
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• v.18 no.6
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• pp.542-548
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• 2007

• Proceedings of the KWS Conference
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• 2002.10a
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• pp.439-449
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• 2002

This paper reviews our recent research works on the interconnection technologies in electronic packaging and assembly. At the aspect of advanced joining methods, laser-ultrasonic fluxless soldering technology was proposed. The characteristic of this technology is that the oxide film was removed through the vibration excitated by high frequency laser change in the molten solder droplet. Application researches of laser soldering technology on solder bumping of BGA packages were carried out. Furthermore, interfacial reaction between SnPb eutectic solder and Au/Ni/Cu pad during laser reflow was analyzed. At the aspect of soldered joints' reliability, the system for predicting and analyzing SMT solder joint shape and reliability(PSAR) has been designed. Optimization design method of soldered joints' structure was brought forward after the investigation of fatigue failure of RC chip devices and BGA packages under temperature cyclic conditions with FEM analysis and experimental study. At the aspect of solder alloy design, alloy design method based on quantum was proposed. The macroproperties such as melting point, wettability and strength were described by the electron parameters. In this way, a great deal of the experimental investigations was replaced, so as to realize the design and research of any kinds of solder alloys with low cost and high efficiency.