• Title/Summary/Keyword: Electromagnetic bias

Search Result 168, Processing Time 0.029 seconds

Design and Fabrication of 0.25 μm CMOS TIA Using Active Inductor Shunt Peaking (능동형 인덕터 Shuut Peaking을 이용한 0.25 μm CMOS TIA 설계 및 제작)

  • Cho In-Ho;Lim Yeongseog
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.16 no.9 s.100
    • /
    • pp.957-963
    • /
    • 2005
  • This paper presents technique of wideband TIA for optical communication systems using TSMC 0.25 ${\mu}m$ CMOS RF-Mixed mode. In order to improve bandwidth characteristics of an TIA, we use active inductor shunt peaking to cascode and common-source configuration. The result shows the 37 mW and 45 mW power dissipation with 2.5 V bias and 61 dB$\Omega$ and 61.4 dB$\Omega$ transimpedance gain. And the -3 dB bandwidth of the TIA is enhanced from 0.8 GHz to 1.45 GHz in cascode and 0.61 GHz to 0.9 GHz in common-source. And the input noise current density is $5 pA/\sqrt{Hz}$ and $4.5 pA/\sqrt{Hz}$, and -10 dB out put return loss is obtained in 1.45 GHz. The total size of the chip is $1150{\times}940{\mu}m^2$.

A High Tunable Capacitor Embedding Its Electrodes in Tunable Thin Film Dielectrics (가변형 박막 유전체에 전극을 임베디드 시킨 고가 변형 커패시터)

  • Lee Young-Chul;Hong Young-Pyo;Ko Kyung-Hyun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.17 no.9 s.112
    • /
    • pp.860-865
    • /
    • 2006
  • In this paper, a novel tunable inter-digital capacitor using dielectric tunable $Bi_2O_3-ZnO-Nb_2O_5(BZN)$ pyrochlore thin films is proposed. In order to improve the tunability and reduce DC bias voltage using the fringing electric field, the electrodes of the inter-digital capacitor are embedded in the thin film. Designed results using a 2.5 D simulator show that the tunability of the proposed inter-digital capacitor improves by 10 %, compared to the conventional inter-digital capacitor. The proposed IDC, which is based on the simulation results, was fabricated, using the BZN thin film deposited by a reactive RF magnetron sputtering on the on the silicon substrate. The fabricated inter-digital capacitor shows the maximum tunability of 50 % at 5.8 GHz and 18 V DC applied.

4H-SiC MESFET Large Signal Modeling using Modified Materka Model (Modified Materka Model를 이용한 4H-SiC MESFET 대신호 모델링)

  • 이수웅;송남진;범진욱
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.12 no.6
    • /
    • pp.890-898
    • /
    • 2001
  • 4H-SiC(silicon carbide) MESFET large signal model was studied using modified Materka-Kacprzak large signal MESFET model. 4H-SiC MESFET device simulation have been conducted by Silvaco\`s 2D device simulator, ATLAS. The result is modeled using modified Materka large signal model. simulation and modeling results are -8 V pinch off voltage, under V$\_$GS/=0 V, V$\_$DS/=25 V conditions, I$\_$DSS/=270 mA/mm, G$\_$m/=52.8 ms/mm were obtained. Through the power simulation 2 GHz, at the bias of V$\_$GS/-4 V md V$\_$DS/=25 V, 10 dB Gain, 34 dBm (1dB compression point)output porter, 7.6 W/mm power density, 37% PAE(power added efficiency) were obtained.7.6 W/mm power density, 37% PAE(power added efficiency) were obtained.d.

  • PDF

A New Calibration Method for the Characterization of Microwave Devices (마이크로파 소자 특성화를 위한 새로운 보정 방법)

  • 신헌철;유영길;정의붕;이종악
    • The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.2 no.3
    • /
    • pp.10-16
    • /
    • 1991
  • The error networks due to the measuring systems and the test fixture must be previously calibrated in order to characterize the microwave devices. In this paper, it is presented a new method to characterize the error networks in which only two different microstrip lines are used for the calibration. Once each length of two calibrat- ing microstrip lines is accurately defined, the calibrated data can be easily obtained without acknowledgement for the propagation constant. The end effect is not considered when fabricated the microstrip lines used to calibration. The ATF13736 GaAs MESFET is characterized by means of the calibrating procedure with this method. The range of measuring frequency is 2 to 18 GHz, and the bias voltage and current are $V_{DS}$ =2.5V, $I_{DS}$ =20mA, respectively. Compared the calibrated data with data sheet, it is showed that the magnitude is nearly agreed with each other and the phase is deviated by 0.1 to 12 degrees in lower frequencies.

  • PDF

13.56~915 MHz CMOS Rectifier Using Bootstrapping and Active Body Biasing (부트스트래핑과 능동 몸체 바이어싱을 이용한 13.56~915 MHz용 CMOS 정류기)

  • Jin, Ho Jeong;Cho, Choon Sik
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.26 no.10
    • /
    • pp.932-935
    • /
    • 2015
  • This paper proposes a rectifier using bootstrapping and active body biasing in $0.11{\mu}m$ RF CMOS process. The proposed rectifier employs the full-wave rectifying structure with cross coupling and increases the power conversion efficiency by reducing the threshold voltage and leakage current using bootstrapping and active bias biasing. Also, it has been designed to be applied to a wide range of applications from 13.56 MHz used in wireless power transmission to 915 MHz used in RFID. As a measured result, 80 % of power conversion efficiency is obtained when the input power is 0 dBm at $10k{\Omega}$ load resistance and 13.56 MHz. Also 40 % of power conversion efficiency is shown in 915 MHz.

A Study on the Improvement of Performance in VCO Using In/Out Common Frequency Tuning (입출력 공동 주파수 동조를 통한 VCO의 성능 개선에 관한 연구)

  • Suh, Kyoung-Whoan;Jang, Jeong-Seok
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.21 no.5
    • /
    • pp.468-474
    • /
    • 2010
  • In this paper, a VCHO(Voltage Controlled Harmonic Oscillator) for K-band application has been designed and implemented. The proposed oscillator has a structure of two hair-pin resonators placed on input and output of active device. Using in/out common frequency tuning structure, the VCHO yields some advantages of the enhanced fundamental frequency suppression characteristic as well as the improved output power of second harmonic. According to implementation and measurement results, it was shown that a VCHO provides an output power of -2.41 dBm, a fundamental frequency suppression of -21.84 dBc, and phase noise of -101.44 dBc/Hz at 100 kHz offset. In addition, as for the bias voltage from 0 V to -10 V for the varactor diode, output frequency range of 10.58 MHz is obtained with a power variation of ${\pm}0.19\;dB$ over its frequency range.

A Design of Predistortion Linearizer using 2nd Low Frequency Intermodulation Signal Injection (2차 저주파 혼변조 신호 주입을 이용한 전치 왜곡 선형 화기 설계)

  • Lee, Hyo-A;Lee, Chul-Whan;Jeong, Yong-Chae;Kim, Young;Kim, Chul-Dong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.14 no.9
    • /
    • pp.967-973
    • /
    • 2003
  • This paper presents a new predistortion method which injects the 2nd low-frequency intermodulation signal of RF signals into the input bias line of the amplifier. New 2nd intermodulation signal extraction circuit is also proposed. We have shown that this method can suppress the 3rd IM apparently and sometimes do the 5th IM, through mathematical analysis, then confirmed it with simulation and verified it on the desk test. When the input signal CDMA IS-95 lFA is applied, measured ACPR improvements are 25 dBc, 22.5 dBc, and 6 dBc at 0.885 MHz, l.25 MHz and 2.25 MHz offset respectively. Also, when applying the CDMA IS-95 3FA, the measured ACPR improvement is 20 dBc at 0.885 MHz offset.

Microwave Group Delay Time Adjuster Using Resonance Circuit (공진 회로를 이용한 마이크로파 군지연 시간 조정기)

  • Seo Su-Jin;Park Sang-Keun;Choi Heung-Jae;Jeong Yong-Chae;Yun Jae-Hun;Kim Chul-Dong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.17 no.8 s.111
    • /
    • pp.739-745
    • /
    • 2006
  • This paper presents a method to control group delay tine using a resonance circuit. The group delay time adjuster(GDTA) that can control signal group delay time comprises a variable capacitance and a variable equivalent inductor. These are coupled in parallel at a node and also controlled by two bias voltages separately, A variable equivalent inductor is realized a transmission line terminated a variable capacitor. Group delay time can be controlled by change of capacitance and inductance, but the resonating frequency is fixed. When the proposed GDTA is fabricated on RFID Korean frequency band$(908.5{\sim}914 MHz)$, a group delay variation is obtained about 3 ns.

A Study on the Design of Dual-Band Mixer for WLAN 802.11a/b/g Applications (802.11a/b/g WLAN용 이중대역 혼합기 설계에 관한 연구)

  • Park Wook-Ki;Go Min-Ho;Kang Suk-Youb;Park Hyo-Dal
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.16 no.11 s.102
    • /
    • pp.1106-1113
    • /
    • 2005
  • This paper presents a dual-band mixer for multi-standards of IEEE 802.1la/b/g using a single local oscillator, so as to improve the defects of legacy systems. Those systems have duplicate local oscillators and mixers to handle dual band signals, increasing complexity of system and power loss. The proposed circuit shows 11.6 dB, 16.8 dB of conversion loss and 8.77 dBm, 12.5 dBm of IIP3(Input 3rd Intercept Point) for respective bands when the two RF inputs of 2.452 and 5.260 GHz are down-converted to the identical 356 MHz If frequency. The RF-LO isolations are measured 36 dB, 41 dB at each frequencies and over 50 dB of LO-IF isolations are achieved at all cases.

A Study on the 8W High Power Amplifier for VSAT at Ku-band (Ku-band의 소형 지구국용을 위한 8W 고출력 증폭기에 관한 연구)

  • 조창환;이찬주;홍의석
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.7 no.1
    • /
    • pp.53-60
    • /
    • 1996
  • The 8W hybrid MIC SSPA has been developed in the frequency range from 14.0 GHz to 14.5 GHz for uplink of KOREASAT's earth station. The whole system was designed of two parts with driving amplifier and high power amplifier to simplify the fabrication process. we reduced weight and volum of power amplifier through arranging the bias circuits in the same housing. The realized SSPA has a small signal gain of $26\pm1dB$within 500 MHz bandwidith, and the input and output return losses are over 7dB and 12dB respectively. The output power of 39.0 ~ 39.2dBm is achieved at the 1dB gain compression point of 14 GHz, 14.25 GHz, and 14.5 GHz. That reveals higher power than 8W of design target. The proposed SSPA manufacture techni- ques in this paper can be applied to the implementation of power amplifiers for some radars and SCPC.

  • PDF