• Journal of IKEEE
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• v.24 no.3
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• pp.890-894
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• 2020

In this paper, we propose an ESD protection device with improved electrical characteristics through structural changes of LVTSCR, a typical ESD protection device. The proposed ESD protection device has a higher holding voltage than the existing LVTSCR by inserting a long N+ drift region and additional P-Well and N-Well, and improves the latch-up immunity, a chronic disadvantage of a general SCR-based ESD protection device. In addition, the effective base width of parasitic BJTs was set as a design variable, and the electrical characteristics of the proposed ESD protection device were verified through Synopsys' TCAD simulation so that it can be applied to the required application by applying the N-Stack technology.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• Journal of IKEEE
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• v.26 no.1
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• pp.119-123
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• 2022

This paper propose a new ESD protection device suitable for 12V class applications by adding a self-biasing structure to an ESD protection device with high holding voltage due to additional parasitic bipolar BJT. To verify the operating principle and electrical characteristics of the proposed device, current density simulation and HBM simulation were performed using Synopsys' TCAD Simulation, and the operation of the additional self-biasing structure was confirmed. As a result of the simulation, it was confirmed that the proposed ESD protection device has a higher level of holding voltage compared to the existing ESD protection device. It is expected to have high area efficiency due to the dual structure and sufficient latch-up immunity in 12V-class applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.288-292
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• 2002

We propose the new type of on-chip ESD protection method for RF applications. By using the properties of RF circuits, we can use the short-circuited stub as ESD protection device in front of the DC blocking capacitor Specially, we can use short-circuited stub as the portion of the matching circuit so to reduce the and various parameters of the transmission line. This new type ESD protection method is very different from the conventional ESD protection method. With the new type ESD protection method, we remove the parasitic capacitance of ESD protection device which degrade the performance of core circuit.

• Journal of IKEEE
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• v.25 no.1
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• pp.168-173
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• 2021

In this paper, we propose a new structure of ESD protection device that achieves improved electrical characteristics through structural change of LVTSCR, which is a general ESD protection device. In addition, it applies N-Stack technology for optimized design in the ESD Design Window according to the required voltage application. The N-Well area additionally inserted in the existing LVTSCR structure provides an additional ESD discharge path by electrically connecting to the anode, which improves on-resistance and temperature characteristics. In addition, the short trigger path has a lower trigger voltage than the existing LVTSCR, so it has excellent snapback characteristics. In addition, Synopsys' T-CAD Simulator was used to verify the electrical characteristics of the proposed ESD protection device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.339-344
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• 2014

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.172-180
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• 2003

Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF ICs. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/40 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD.

• Journal of IKEEE
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• v.23 no.4
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• pp.1309-1313
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• 2019

In this paper, the electrical characteristics of Gate grounded NMOS(GGNMOS), Lateral insulated gate bipolar transistor(LIGBT), Silicon Controlled Rectifier(SCR), and Proposed ESD protection device were compared and analyzed. First, the trigger voltage and holding voltage were verified by simulating the I-V characteristic curve for each device. After that, the robustness was confirmed by HBM 4k simulation for each device. As a result of HBM 4k simulation, the maximum temperature of the proposed ESD protection device is lower than that of GGNMOS and GGLIGBT and SCR, which means that the robustness is improved, which means that the ESD protection device is excellent in terms of reliability.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1370-1371
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• 2006

An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latchup problem during normal operation. However, a modified NEDSCR device with proper junction / channel engineering demonstrates itself with both the excellent ESD protection performance and the high latchup immunity.

• Journal of the Semiconductor & Display Technology
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• v.6 no.4
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• pp.53-57
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• 2007

In paper, We evaluated for various diode type ESD protection device using TLP measurement method. An Evaluation diode is divided to Enclosed type and Stripe type as pattern style in extensive. These diodes is split up followed factor that Anode-to-Cathod space, N+ region width, Multi type and Contact to Active space. After a TLP measurement, we can be got the Vt2, It2 by I-V characteristic values. In the results, diode of enclosed type is present relatively higher Current capability(It2) than stripe type in a same voltage conditions. And the Second-breakdown voltage(Vt2) were that Stripe type's diode higher than Enclosed type's diode as have $14{\sim}15V$. Finally we suggest the best diode design condition as ESD protection device using entire consequence.