• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.674-676
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• 2008

An electrostatic discharge (ESD) or a noise supplied from the outside has an effect on communication between the timing controller (TCON) and the memory element (EEPROM) through the interface between the timing controller and the memory element in liquid crystal displays (LCD). Therefore, we must apply ESD protection methods to LCD operating circuits for a normal operation. Our ESD protection circuit is to prevent from bi-directional communication errors between TCON and EEPROM due to an electrostatic discharge (ESD).

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.153-166
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• 2003

Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.908-910
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• 2007

Thin Film Transistor (TFT) manufacturing process is complicated. Electrostatic discharge (ESD) occurs during every process step. This paper describes ESD phenomena in terms of TFT design and processing flow. The abnormal contact between equipment and glass is found out to be the key reason causing ESD.

• Journal of the Korean Society of Safety
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• v.17 no.4
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• pp.94-100
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• 2002

As the use of automatic handling equipment for sensitive semiconductor devices is rapidly increased, manufacturers of electronic components and equipments need to be more alert to the problem of electrostatic discharges(ESD). In order to analyze damage characteristics of semiconductor device damaged by ESD, this study adopts a new charged-device model(CDM), field-induced charged model(FCDM) simulator that is suitable for rapid, routine testing of semiconductor devices and provides a fast and inexpensive test that faithfully represents ESD hazards in plants. High voltage applied to the device under test is raised by the field of non-contacting electrodes in the FCDM simulator, which avoids premature device stressing and permits a faster test cycle. Discharge current and time are measured and calculated. The characteristics of electrostatic attenuation of domestic semiconductor devices are investigated to evaluate the ESD phenomena in the semiconductors. Also, the field charging mechanism, the device thresholds and failure modes are investigated and analyzed. The damaged devices obtained in the simulator are analyzed and evaluated by SEM. The results obtained in this paper can be used to prevent semiconductor devices form ESD hazards and be a foundation of research area and industry relevant to ESD phenomena.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1289-1294
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• 2008

Electrostatic discharge(ESD) phenomenon is a serious reliability concern. It causes approximately most of all field failures of IC. To quality the ESD immunity of IC product, there are some test methods and standards developed. ESD events have been classified into 3 models, which are HBM, MM and CDM. All the test methods are designed to evaluate the ESD immunity of IC products. This study provides an overview among ESD test methods on ICs and an efficient ESD stress method. We have estimated on all pin combination about the positive and negative ESD stress. We make out the weakest stress mode. This mode called a worst-case mode. We proposed that positive supply voltage pin and I/O pin combination is efficient because it is a worst-case mode.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.24-25
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• 2008

An Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics, especially for RF (Radio Frequency) integrated circuits (ICs). This paper reviews design and analysis of on-chip ESD (electrostatic discharge) protection circuits for RF applications. Key issues in RF ESD protection, design methods, and RF ESD protection solutions are discussed.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.2017-2032
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• 2018

This study presents, for the first time, state-of-the art review of the various techniques for the modeling of the electrostatic discharge (ESD) generators for the ESD analysis and testing. After a brief overview of the ESD generator, the study provides an in-depth review of ESD generator modeling (analytical, circuit and numerical modeling) techniques for the contact discharge mode. The proposed techniques for each modeling approach are compared to illustrates their differences and limitations.

• Journal of the Korean Magnetics Society
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• v.12 no.5
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• pp.168-173
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• 2002

Electrostatic discharge characteristics were studied by connecting human body model (HBM) with tunneling magnetoresistance (TMR) device in this research. TMR samples were converted into electrical equivalent circuit with HBM and it was simulated utilizing PSPICE. Discharge characteristics were observed by changing the component values of the junction model in this equivalent circuit. The results show that resistance and capacitance of the TMR junction were determinative components that dominate the sensitivity of the electrostatic discharge(ESD). Reducing the resistance oi the junction area and lead line is more profitable to increase the recording density rather than increasing the capacitance to improve the endurance for ESD events. Endurance at DC state was performed by checking breakdown and failure voltages for applied DC voltage. HBM voltage that a TMR device could endure was estimated when the DC failure voltage was regarded as the HBM failure voltage.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.2033-2044
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• 2018

This study presents states-of-the art overview of the system level electrostatic discharge (ESD) analysis and testing. After brief description of ESD compliance standards and ESD coupling mechanisms, the study provides an in-depth review and comparison of the various techniques for the system level ESD coupling analysis using time and frequency domain techniques, full wave electromagnetic modeling and hybrid modeling. The methods used for improving system level ESD testing using troubleshooting and determining the root causes of soft failures, the optimization of ESD testing and the countermeasures to mitigate ESD problems are also discussed.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.195-201
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• 2014

In this paper, we developed a LGP(Light Guide Panel) dry cleaning system for particle cleaning using corona discharge and dry adhesive roll. Therefore, we design a cleaning mechanism that can be applied dry adhesive dust removal roll and ESD(electrostatic discharge) by using corona discharge. Also, we design and implementation of equipment, which can loading, unloading and transfer LGP automatically. The developed equipment is dust and particle cleaning experimental results to demonstrate its stability.