• Journal of Applied Reliability
• /
• v.11 no.3
• /
• pp.245-249
• /
• 2011

Through the test of ESD(Electro Static Discharge) for PCB circuit, we are able to research on the ESD effect. This paper also studys on the ESD test method for measurement. In the measurement of the discharge current, we used current probe(TC-1). The applied voltage to the PCB metal is -3 kV HBM mode. In conclusion ESD influences exponentially greater impact in nearer PCB circuit.

• Journal of the Korea Convergence Society
• /
• v.8 no.8
• /
• pp.77-82
• /
• 2017

In the splay manufacturing process, conveyor systems are widely used for conveying panels. In this conveyor, a large number of grounding lines are used in order to prevent a product failure due to static electricity. In many cases, the grounding line is disconnected due to the rotation of the transporting roller or curling, leading to product failure. In order to solve such a problem, there is a growing need for a system capable of detecting disconnection of a ground wire in real time. Therefore, in this paper, we propose a disconnection monitoring system of ESD (Electro-Static Discharge) ground wire caused by friction between the conveyor drive part and the panel. The proposed system is a monitoring system that can detect disconnection and disconnection of ground wire using ATmega 2560 and Wheatstone Bridge circuit. It can detect disconnection of ground wire immediately and can take measures to reduce the defect rate due to static electricity. The system proposed in this paper is expected to be applicable to the production and test equipments of all industries where the ground wire is used.

• Journal of IKEEE
• /
• v.10 no.2 s.19
• /
• pp.141-148
• /
• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.256-257
• /
• 2007

정전기방전(Electro-Static Discharge)에 의한 피해는 전기전자제품의 파괴, 분체의 유도성 폭발, 도장 시 화재 등의 산업 각 분야에 걸쳐 인명이나 물질적 형태로 방대하게 발생하고 있다. 본 논문에서는 이와 같은 여러 형태의 ESD 피해형태 중 전기전자제품 관련분야에 대한 국내외적인 동향을 소개하고자 한다. 반도체, 디스플레이, 등 전기전자 산업분야의 소형화, 고속화는 ESD에 대한 민감도를 증가시키고 있으며, 전기전자 환경의 모든 산업분야에서 제품의 생산성, 신뢰성, 안전성에 커다란 영향을 미치고 있다. 그러므로 ESD 관련 국내 산업의 피해실태와 원인, ESD 방지를 위한 국내기술의 수준을 파악하고, 국제적인 기술동향을 분석하는 것은 매우 중요한 일이다. 이를 바탕으로 한 국내 관련 산업의 국제적인 경쟁력 확보를 위한 국가차원의 관리시스템 및 교육제도 도입성의 필요성을 제시하고자 한다.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.731-734
• /
• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at the same time. Maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, we performed the layout high speed I/O interface circuit with the low triggered ESD protection device in one-chip.

• Journal of IKEEE
• /
• v.10 no.2 s.19
• /
• pp.149-155
• /
• 2006

In this study, the design of low voltage DC-DC converter with low triggering ESD (Electro-Static Discharge) protection circuit was investigated. The purpose of this paper is design optimization for low voltage(2.5V to 5.5V input range) DC-DC converter using CMOS switch. In CMOS switch environment, a dominant loss component is not switching loss but conduction loss at 1.2MHz switching frequency. In this study a constant frequency PWM converter with synchronous rectifier is used. And zener Triggered SCR device to protect the ESD phenomenon was designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 8V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.08a
• /
• pp.19-24
• /
• 2002

Static electricity is an everyday phenomenon. There can be few of us who have not experienced a static shock after sliding across a car seat. Other static nuisance effects include the cling of some fabrics to the body, the sticking of a plastic document cover, or the attraction of dust to a TV or computer screen. However, static electricity has been a serious industrial problem. The age of electronics brought with it new problems associated with static electricity and electrostatic discharge. And, as electronic devices became faster and smaller, their sensitivity to ESD increased. In this work, We are study on the control technique of electo-static discharges using semiconductor circuits. Our circuits are prevented well to electrostatic shock or damages from triboelectric charging in cars everyday life.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.12 no.2
• /
• pp.150-154
• /
• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.805-808
• /
• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD(Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at same time. maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps, Also, the LIGCSCR(Latch-up Immune Gate Coupled SCR)was designed. It consists of PLVTSCR (P-type Low Voltage Trigger SCR), control NMOS and RC network. The triggering voltage was simulated to 3.6V. And the latch-up characteristics were improved. Finally, we performed the layout high speed I/O interlace circuit with the low triggered ESD protection device in one-chip.

• Journal of IKEEE
• /
• v.13 no.1
• /
• pp.87-93
• /
• 2009

The paper introduces a silicon controlled rectifier (SCR)-based device with high holding voltage for ESD power clamp. The holding voltage can be increased by extending a p+ cathode to the first n-well and adding second n-well wrapping around n+ cathode. The increase of the holding voltage above the supply voltage enables latch-up immune normal operation. In this study, the proposed device has been simulated using synopsys TCAD simulator for electrical characteristic, temperature characteristic, and ESD robustness. In the simulation result, the proposed device has holding voltage of 3.6V and trigger voltage of 10.5V. And it is confirmed that the device could have holding voltage of above 4V with the size variation of extended p+ cathode and additional n-well.