• Title/Summary/Keyword: Dual PLL

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A Continuously Tunable LC-VCO PLL with Bandwidth Linearization Techniques for PCI Express Gen2 Applications

  • Rhee, Woo-Geun;Ainspan, Herschel;Friedman, Daniel J.;Rasmus, Todd;Garvin, Stacy;Cranford, Clay
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.3
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    • pp.200-209
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    • 2008
  • This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-GHz PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dual-path VCO is important for deterministic jitter (DJ) performance.

Design of the Charge pump PLL using Dual PFD (듀얼 위상 주파수 검출기를 이용한 차지펌프 PLL 설계)

  • Lee, Jun-Ho;Lee, Geun-Ho;Son, Ju-Ho;Kim, Sun-Hong;Yu, Young-Gyu;Kim, Dong-Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.8
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    • pp.20-26
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    • 2001
  • In this paper, the charge pump PLL using the dual PFD to improve the trade-off between acquisition behavior and locked behavior is proposed. This dual PFD consists of a positive edge triggered PFD and a negative edge triggered PFD. The proposed charge pump shows that it is possible to overcome the issue of the charge pump current imsmatch by the current subtraction circuit. Also, this charge pump can suppress reference spurs and disturbance of the VCO control voltage. The proposed charge pump PLL is simulated by SPICE using 0.25${\mu}m$ CMOS process parameters.

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A Dual-compensated Charge Pump for Reducing the Reference Spurs of a Phase Locked Loop (위상 고정 루프의 기준 스퍼를 감소시키기 위한 이중 보상 방식 전하 펌프)

  • Lee, Dong-Keon;Lee, Jeong-Kwang;Jeong, Hang-Geun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.2
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    • pp.465-470
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    • 2010
  • The charge pump in a phase-locked loop is a key block in determining reference spurs of the VCO output signal. To reduce reference spurs, the current mismatch in the charge pump must be minimized. This paper presents a dual compensation method to reduce the current mismatch. The proposed charge pump and PLL were realized in a $0.18{\mu}m$ CMOS process. Measured current matching characteristics were achieved with less than 1.4% difference and with the current variation of 3.8% in the pump current over the charge pump output voltage range of 0.35-1.35V at 1.8V. The reference spur of the PLL based on the proposed charge pump was measured to be -71dBc.

(A Dual Type PFD for High Speed PLL) (고속 PLL을 위한 이중구조 PFD)

  • 조정환;정정화
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.39 no.1
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    • pp.16-21
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    • 2002
  • In this paper, a dual type PFD(Phase Frequency Detector) for high speed PLL to improve output characteristics using TSPC(True Single Phase Clocking) circuit is proposed. The conventional 3-state PFD has problems with large dead-zone and long delay time. Therefore, it is not applicable to high-speed PLL(Phase-Locked Loop). A dynamic PFD with dynamic CMOS logic circuit is proposed to improve these problems. But, it has the disadvantage of jitter noise due to the variation of the duty cycle. In order to solve the problems of previous PFD, the proposed PFD improves not only the dead zone and duty cycle but also jitter noise and response characteristics by the TSPC circuit and dual structured PFD circuit. The PFD is consists of a P-PFD(Positive edge triggered PFD) and a N-PFD(Negative edge triggered PFD) and improves response characteristics to increase PFD gain. The Hspice simulation is performed to evaluate the performance of proposed PFD. From the experimental results, it has the better dead zone, duty cycle and response characteristics than conventional PFDs.

A novel PLL control method for robust three-phase thyristor converter under sag and notch conditions

  • Lee, Changhee;Yoo, Hyoyol
    • Proceedings of the KIPE Conference
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    • 2014.11a
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    • pp.87-88
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    • 2014
  • The paper presents a novel phase locked loop(PLL) control method for robust three-phase thyristor dual converters under sag, notch, and phase loss conditions. This method is applied to three line to line voltages of grid to derive three phase angle errors from three separated single-phase PLLs. They can substitute for abnormal phase to guarantee the synchronization in the various grid fault conditions. The performance of novel PLL with moving average method is verified through simulations.

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A New Phase-Locked Loop System with the Controllable Output Phase and Lock-up Time

  • Vibunjarone, Vichupong;Prempraneerach, Yothin
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1836-1840
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    • 2003
  • This paper, we propose a new phase-locked loop (PLL) system with the controllable output phase, independent from the output frequency, and lock-up time. This PLL system has a dual control loop is described, the inner loop greatly improved VCO characteristic such as faster speed response as well as higher operation bandwidth, to minimize the effect of the VCO noise and the power supply variation and also get better linearity of VCO output. The main loop is the heart of this PLL which greatly improved the output frequency instability due to the external high frequency noise coupling to the input reference frequency also the main loop can control the output phase, independent from the output frequency, and reduce the lock-up time of the step frequency response. The experimental results confirm the validity of the proposed strategy.

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Performance Improvement of Sensorless Drives for Surface Mounted Permanent Magnet Synchronous Motor using a Dual PLL Structure (이중 PLL 구조를 이용한 표면부착형 영구자석 동기전동기 센서리스 구동장치의 성능 개선)

  • Lee, Kwang-Woon
    • The Transactions of the Korean Institute of Power Electronics
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    • v.22 no.6
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    • pp.543-546
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    • 2017
  • This paper presents a simple approach for improving the performance of back-electromotive force (back-EMF)-estimation-based sensorless drives for surface-mounted permanent magnet synchronous motors (SPMSM). Similar to conventional approaches, a hypothetical d-q synchronous reference frame model of SPMSM is employed in the proposed approach to estimate the back-EMFs. This approach also employs a dual phase locked loop structure to compensate for the effect of the dead time and parameter uncertainty of the inverter on the estimated back-EMFs. The proposed algorithm is validated by conducting experiments.

A Design of PLL for 6 Gbps Transmitter in Display Interface Application (디스플레이 인터페이스에 적용된 6 Gbps급 송신기용 PLL(Phase Locked Loop) 설계)

  • Yu, Byeong-Jae;Cho, Hyun-Mook
    • Journal of IKEEE
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    • v.17 no.1
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    • pp.16-21
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    • 2013
  • Recently, frequency synthesizers are being designed in two ways narrow-band loop or dual-loop for wide-band to reduce the phase noise. However, dual-loop has the disadvantage of center frequency mismatch and requiring an extra loop. In this paper, we propose a new structure that supports a range of 800Mhz ~ 3Ghz with multiple control of the single-loop frequency synthesizer without another loop. The control voltage of the VCO(coarse, fine) will be fixed, and finally the VCO will have a low Kvco. The frequency synthesizer is simulated using UMC $0.11{\mu}m$ process, proposed frequency synthesizer can be used in a variety of applications in the future.

A Dual Charge Pump PLL-based Clock Generator with Power Down Schemes for Low Power Systems (저 전력 시스템을 위한 파워다운 구조를 가지는 이중 전하 펌프 PLL 기반 클록 발생기)

  • Ha, Jong-Chan;Hwang, Tae-Jin;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.11
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    • pp.9-16
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    • 2005
  • This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

A Design and Fabrication of Low Phase Noise Frequency Synthesizer Using Dual Loop PLL (이중루프 PLL을 이용한 IMT-2000용 저 위상잡음 주파수 합성기의 설계 및 제작)

  • Kim, Kwang-Seon;Choi, Hyun-Chul
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.2C
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    • pp.191-200
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    • 2002
  • A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.