The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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A Dual-compensated Charge Pump for Reducing the Reference Spurs of a Phase Locked Loop

위상 고정 루프의 기준 스퍼를 감소시키기 위한 이중 보상 방식 전하 펌프

  • 이동건 (전북대학 전자정보공학부) ;
  • 이정광 (전북대학 전자정보공학부) ;
  • 정항근 (전북대학 전자정보공학부)
  • Published : 2010.02.01
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Abstract

The charge pump in a phase-locked loop is a key block in determining reference spurs of the VCO output signal. To reduce reference spurs, the current mismatch in the charge pump must be minimized. This paper presents a dual compensation method to reduce the current mismatch. The proposed charge pump and PLL were realized in a $0.18{\mu}m$ CMOS process. Measured current matching characteristics were achieved with less than 1.4% difference and with the current variation of 3.8% in the pump current over the charge pump output voltage range of 0.35-1.35V at 1.8V. The reference spur of the PLL based on the proposed charge pump was measured to be -71dBc.

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References

  1. Dao-Lon Chen, "Designing On-Chip Clock Generators," in Circuits and Devices, pp. 32-36, Jul. 1992.
  2. F. Gardner, "Charge-Pump Phase-Locked Loops," IEEE Trans. Communications, vol. com-28, no. 11, pp. 1849-1858, Nov. 1980.
  3. W. Rhee, "Design of high-performance CMOS charge pumps in phase-locked loops," in Proc. ISCAS, Vol. 2, pp. 542-548, Orlando, FL. USA, July 1999.
  4. W. Rhee, Bang-Sup Song, Akbar Ali, "A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ${\Delta}{\Sigma}$ modulator," IEEE J. Solid-State Circuits, Vol. 35, no. 10, pp. 1453-1460, Oct. 2000. https://doi.org/10.1109/4.871322
  5. Young-Shig Choi, Dae-Hyun Han, "Gain-boosting charge pump for current matching in phase-locked loop", IEEE Trans. Circuits Syst. II, Express Briefs, Vol. 53, no. 10, pp. 1022-1025, Oct. 2006. https://doi.org/10.1109/TCSII.2006.882122
  6. Lee J.S., Keel M. S., Lim S. I., and Kim S., "Charge pump with perfect current matching characteristics in phase-locked loops", IEEE Electronics Lett., Vol. 36, no. 23, pp. 1907-1908, Nov. 2000. https://doi.org/10.1049/el:20001358
  7. A. Maxim, "A 0.16-2.55 GHz CMOS active clock deskewing PLL using analog phase interpolation," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 110-131, Jan. 2005. https://doi.org/10.1109/JSSC.2004.838004
  8. P. Larsson, A. Chen, "A Frequency Programmable Clock Extraction Chip," The 5th VLSI/CAD Symposium, Taiwan, R.O.C. 1994.