• Journal of IKEEE
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• 제26권3호
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• pp.333-340
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• 2022

Process and device simulations were performed to determine the optimal ion implantation conditions to prevent double snapback of high voltage operating DDDNMOS (double diffused drain N-type MOSFET) device for ESD protection. By examining the effects of HP-Well, N^- drift and N⁺ drain ion implantation on the double snapback and avalanche breakdown voltages, it was possible to prevent double snapback and improve the electrostatic protection performance. If the ion implantation concentration of the N^- drift region rather than the HP-Well region is optimally designed, it prevents the transition from the primary on-state to the secondary on-state, so that relatively good ESD protection performance can be obtained. Since the concentration of the N^- drift region affects the leakage current and the avalanche breakdown voltage, in the case of a process technology with an operating voltage greater than 30V, a new structure such as DPS or colligation of optimal process conditions can be applied. In this case, improved ESD protection performance can be realized.

• Proceedings of the Korean Vacuum Society Conference
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제19권12호
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• pp.2892-2898
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• 2015

We propose a new Double-Independent-Gate Ambipolar Silicon-Nanowire Field Effect Transistor(DIG Ambi-SiNWFET). The proposed transistor has two types of gate such as polarity gate and control gate. The polarity gate determines the operation that the gate bias controls NMOSFET or PMOSFET. The voltage of control gate controls the current characteristic of the transistor. We investigated systematically work functions of the two gates and source/drain to operate ambipolar current-voltage characteristics using 2D device simulator. When the work functions of polarity gate, control gate and source/drain are 4.75eV, 4.5eV, and 4.8eV, respectively, it showed the obvious ambipolar characteristics.

• Korean Journal of Materials Research
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• 제13권1호
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• pp.43-47
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• 2003

As and BF$_2$dopants are implanted for the formation of source/drain with dose of 1${\times}$10$^{15}$ ions/$\textrm{cm}^2$∼5${\times}$10$^{15}$ ions/$\textrm{cm}^2$ then formed cobalt disilicide with Co/Ti deposition and doubly rapid thermal annealing. Appropriate ion implantation and cobalt salicide process are employed to meet the sub-0.13 $\mu\textrm{m}$ CMOS devices. We investigated the process results of sheet resistance, dopant redistribution, and surface-interface microstructure with a four-point probe, a secondary ion mass spectroscope(SIMS), a scanning probe microscope (SPM), and a cross sectional transmission electron microscope(TEM), respectively. Sheet resistance increased to 8%∼12% as dose increased in $CoSi_2$$n^{＋}$ and $CoSi_2$$p^{V}$ , while sheet resistance uniformity showed very little variation. SIMS depth profiling revealed that the diffusion of As and B was enhanced as dose increased in $CoSi_2$$n^{＋}$ and $CoSi_2$$p^{＋}$ . The surface roughness of root mean square(RMS) values measured by a SPM decreased as dose increased in $CoSi_2$$n^{＋}$ , while little variation was observed in $CoSi_2$$p^{＋}$ . Cross sectional TEM images showed that the spikes of 30 nm∼50 nm-depth were formed at the interfaces of $CoSi_2$$n^{＋}$ / and $CoSi_2$/$p^{＋}$, which indicate the possible leakage current source. Our result implied that Co/Ti cobalt salicide was compatible with high dose sub-0.13$\mu\textrm{m}$ process.

• Journal of Sensor Science and Technology
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• 제23권2호
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• pp.114-121
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• 2014

We report a polysilicon active area membrane field effect transistor (PSAFET) pressure sensor for low stress deflection of membrane. The PSAFET was produced in conventional FET semiconductor fabrication and backside wet etching. The PSAFET located at the front side measured pressure change using 300 nm thin-nitride membrane when a membrane was slightly strained by the small deflection of membrane shape from backside with any physical force. The PSAFET showed high sensitivity around threshold voltage, because threshold voltage variation was composed of fractional function form in sensitivity equation of current variation. When gate voltage was biased close to threshold voltage, a fractional function form had infinite value at $V_{tn}$, which increased the current variation of sensitivity. Threshold voltage effect was dominant right after the PSAFET was turned on. Narrow transistor channel established by small current flow was choked because electron could barely cross drain-source electrodes. When gate voltage was far from threshold voltage, threshold voltage effect converged to zero in fractional form of threshold voltage variations and drain current change was mostly determined by mobility changes. As the PSAFET fabrication was compatible with a polysilicon FET in CMOS fabrication, it could be adapted in low pressure sensor and bio molecular sensor.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제27권3호
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• pp.55-64
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• 2013

In this paper, a new topology which can add a small reactor in series to a condenser-bank type reactive power compensator to limit current is proposed. And also the proposed topology can add or remove a power condenser safely without any addition of inrush-current suppression resistance. The proposed method tests variable resistance of the drain source of a switching device which is controlled by gate voltage in a two-way switch with a diode rectifier and FET switch. In other words, the proposed method is a inrush-current suppression method with the structure of variable resistance. In particular, the proposed method creates smooth current without any resonance in inrush-current as well as is not limited by the time of switch on and off.

• Advances in nano research
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• 제3권1호
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• pp.49-54
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• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제19권6호
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• pp.1399-1404
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• 2015

This paper analyzed the phenomenon of drain induced barrier lowering(DIBL) for the ratio of channel length vs. thickness of asymmetric double gate(DG) MOSFET. DIBL, the important secondary effect, is occurred for short channel MOSFET in which drain voltage influences on potential barrier height of source, and significantly affects on transistor characteristics such as threshold voltage movement. The series potential distribution is derived from Poisson's equation to analyze DIBL, and threshold voltage is defined by top gate voltage of asymmetric DGMOSFET in case the off current is 10^-7 A/m. Since asymmetric DGMOSFET has the advantage that channel length and channel thickness can significantly minimize, and short channel effects reduce, DIBL is investigated for the ratio of channel length vs. thickness in this study. As a results, DIBL is greatly influenced by the ratio of channel length vs. thickness. We also know DIBL is greatly changed for bottom gate voltage, top/bottom gate oxide thickness and channel doping concentration.

• Journal of the Korean Institute of Telematics and Electronics
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• 제26권11호
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• pp.1706-1711
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• 1989

Unit processes for the fabrication of HEMT(high electron mobility transistor)was studied and the optimum conditions of them were applied to the fabrifcation of a discrete HEMT device. The HEMT with a nominal gate-source spacing of 3.6\ulcorner and a gate length of 2.8\ulcorner showed a transconductance of 46.1mS/mm and a threshold voltage of -0.29V. A source-drain voltage of 2.0V for a saturation current of 35mA/mm was achieved.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2004년도 학술대회지
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• pp.787-791
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• 2004

We investigated field-effect ion-transport devices based on carbon nanotubes by using classical molecular dynamics simulations under applied external force fields, and we present model schematics that car be applied to the nanoscale data storage devices and unipolar ionic field-effect transistors. As the applied external force field is increased, potassium ions rapidly flow through the nanochannel. Under low external force fields, ther nal fluctuations of the nanochannels affect tunneling of the potassium ions whereas the effects of thermal fluctuations are negligible under high external force fields. Since the electric current conductivity increases when potassium ions are inserted into fullerenes or carbon nanotubes, the field effect due to the gate, which can modify the position of the potassium ions, changes the tunneling current between the drain and the source.