• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1494-1495
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• 2009

Thin Film Transistor(TFT) having CIS (CuInSe) semiconductor layer was fabricated and characterized. Heavily doped Si was used as a common gate electrode and PECVD Silicon nitride ($SiN_x$) was used as a gate dielectric material for the TFT. Source and drain electrodes were deposited on the $SiN_x$ layer and CIS layer was formed by a direct patterning method between source and drain electrodes. Nanoparticle of CIS material was used as the ink of the direct patterning method.

• E2M - 전기 전자와 첨단 소재
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• 제9권10호
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• pp.1001-1007
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• 1996

The conduction mechanisms of the off-current in low temperature (.leq. >$600^{\circ}C$) processed polycrystalline silicon thin film transistors (LTP poly-Si TFT'S) have been systematically studied. Especially, the temperature and bias dependence of the off-current between hydrogenated and nonhydrogenated poly-Si TFT's were investigated and compared. The off-current of nonhydrogenated poly-Si TF's is because of a resistive current at low gate and drain voltage, thermally activated current at high gate and low drain voltage, and Poole-Frenkel emission current in the depletion region near the drain at high gate and drain voltage. After hydrogenation it has shown that the off -current mechanism is caused mainly by thermal activation and that the field-induced current component is suppressed.

• E2M - 전기 전자와 첨단 소재
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• 제8권5호
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• pp.626-632
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• 1995

In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

• Transactions on Electrical and Electronic Materials
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• 제12권6호
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• pp.271-274
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• 2011

Screen-printed source and drain electrodes were used for a spin-coated and inkjet-processed zinc-tin oxide (ZTO) TFTs for the first time. Source and drain were silver nanoparticles. Channel length was patterned using screen printing technology. Different silver nanoinks and process parameters were tested to find optimal source and drain contacts Relatively good electrical properties of a screen-printed inkjet-processed oxide TFT were obtained as follows; a mobility of 1.20 $cm^2$/Vs, an on-off current ratio of $10^6$, a Vth of 5.4 V and a subthreshold swing of 1.5 V/dec.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.157-157
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• 2008

As the minimum feature size of semiconductor devices scales down to nano-scale regime, ultra shallow junction is highly necessary to suppress short channel effect. At the same time, Ni-silicide has attracted a lot of attention because silicide can improve device performance by reducing the parasitic resistance of source/drain region. Recently, further improvement of device performance by reducing silicide to source/drain region or tuning the work function of silicide closer to the band edge has been studied extensively. Rare earth elements, such as Er and Yb, and Pd or Pt elements are interesting for n-type and p-type devices, respectively, because work function of those materials is closer to the conduction and valance band, respectively. In this paper, we increased the work function between Ni-silicide and source/drain by using Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. We demonstrated that it is possible to control the barrier height of Ni-silicide by adjusting the thickness of Pd layer. Therefore, the Ni-silicide using the Pd stacked structure could be applied for high performance PMOSFET.

• 한국전기전자재료학회논문지
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• 제33권3호
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• pp.169-172
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• 2020

In this paper, the effect of hot carrier injection on an n-bulk fin field-effect transistor (FinFET) is analyzed. The hot carrier injection method is applied to determine the performance change after injection in two ways, channel hot electron (CHE) and drain avalanche hot carrier (DAHC), which have the greatest effect at room temperature. The optimum condition for CHE injection is V_G=V_D, and the optimal condition for DAHC injection can be indirectly confirmed by measuring the peak value of the substrate current. Deterioration by DAHC injection affects not only hot electrons formed by impact ionization, but also hot holes, which has a greater impact on reliability than CHE. Further, we test the amount of drain voltage that can be withstood, and extracted the lifetime of the device. Under CHE injection conditions, the drain voltage was able to maintain a lifetime of more than 10 years at a maximum of 1.25 V, while DAHC was able to achieve a lifetime exceeding 10 years at a 1.05-V drain voltage, which is 0.2 V lower than that of CHE injection conditions.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2013년도 춘계학술대회 논문집
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• pp.154-154
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• 2013

In this work, we investigated the characteristics and the effects of light on the negative gate bias stress stability (NBS) in high mobility polycrystalline IGO TFTs. IGO TFT showed a high drain current on/off ratio of ${\sim}10^9$, a field-effect mobility of $114cm^2/Vs$, a threshold voltage of -4V, and a subthresholdslpe(SS) of 0.28V/decade from log($I_{DS}$) vs $V_{GS}$. IGO TFTs showed large negative $V_{TH}$ shift(17V) at light power of $5mW/cm^2$ with negative gate bias stress of -10V for 10000seconds, at a fixed drain voltage ($V_{DS}$) of 0.5V.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2001년도 추계학술대회 논문집
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• pp.552-557
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• 2001

Copper slag is the by-producted material on the proceeding of refining the copper. To verify applications of copper slag to vertical drain material can substitute for the sands in ground improvement, laboratory soil tests and consolidation model tests were conducted. The results of consolidation model test was analyzed as the hyperbolic method. The hyperbolic method assumes that the settlement(s) versus time(t) behavior approaches a straight line describes a hyperbolic reaction. The inverse of the slope of the line would then yield the ultimate settlement. Through in this study, copper slag is compatible with vertical drain material as like sands. Copper slag compaction pile promote the consolidation settlement.

• Journal of Chest Surgery
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• 제51권4호
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• pp.260-265
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• 2018

Background: A method of wound closure using knotless suture material in the chest tube site has been introduced at our center, and is now widely used as the primary method of closing chest tube wounds in video-assisted thoracic surgery (VATS) because it provides cosmetic benefits and causes less pain. Methods: We included 109 patients who underwent VATS pulmonary resection at Samsung Medical Center from October 1 to October 31, 2016. Eighty-five patients underwent VATS pulmonary resection with chest drain wound closure utilizing knotless suture material, and 24 patients underwent VATS pulmonary resection with chest drain wound closure by the conventional method. Complications related to the chest drain wound were compared between the 2 groups. Results: There were 2 cases of pneumothorax after chest tube removal in both groups (8.3% in the conventional group, 2.3% in the knotless suture group; p=0.172) and there was 1 case of wound discharge due to wound dehiscence in the knotless suture group (0% in the conventional group, 1.2% in the knotless suture group; p=0.453). There was no reported case of chest tube dislodgement in either group. The complication rates were non-significantly different between the 2 groups. Conclusion: The results for the complication rates of this new chest drain wound closure method suggest that this method is not inferior to the conventional method. Chest drain wound closure using knotless suture material is feasible based on the short-term results of the complication rate.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.54-57
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• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.