• 한국ITS학회 논문지
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• 제5권2호
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• pp.55-60
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• 2006

In this paper, a broadband double balanced mixer is presented using a wideband Marchand balun implementation by vertical coupler. Frequency is selected as $1.0{\sim}3.7GHz$ for RF, $1.14{\sim}3.84GHz$ for LO, and 140 MHz for IF signals. When LO signal with 7 dBm at 2.64 GHz is injected, a conversion loss of 7.5 dB and RF to LO isolation of -45 dB are obtained. Also, an average conversion loss of 9 dB and RF to LO isolation of -25 dB are obtained for frequency band of $1.0{\sim}3.7GHz$.

• Journal of electromagnetic engineering and science
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• 제9권2호
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2008년도 정보통신설비 학술대회
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• pp.414-417
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• 2008

This paper presents the design and analysis of 2.45GHz Low-IF Mixer using CMOS 0.18um. The Mixer is implemented by using the Gilbert-type configuration, current bleeding technique, and the resonating technique for the tail capacitance. And the design of this Double Balance Mixer is based on its lineaity since it is important in the interference cancellation system. The low flicker noise mixer is implemented by incorporating a double balanced Gilber-type configuration, the RF leakage-less current bleeding technique, and Cp resonating technique. The proposed mixer has a simulated conversion gain of 16dB a simulated IIP3 of -3.3dBm and P1dB is -19dBm. A simulated noise figure of 6.9dB at l0MHz and a flicker corner frequency of 510kHz while consuming only 10.65mW od DC power. The layout of Mixer for one-chip design in a 0.18-um TSMC process has 0.474mm$\times$0.39 mm size.

• 한국통신학회:학술대회논문집
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• 한국통신학회 2006년도 하계종합학술발표회 논문 초록집
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• pp.718-718
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• 2006

• International journal of advanced smart convergence
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• 제10권1호
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• pp.12-23
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• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

• 한국전자파학회논문지
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• 제15권6호
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• pp.608-618
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• 2004

본 논문에서는 Maas의 die 이중평형혼합기 회로를 개선, 새로운 pHEMT resistive star 이중평형혼합기 회로를 제안하였다. Star 구조로 구성되기 때문에 기존의 FET ring 혼합기 구조와 달리 별도의 IF balun이 필요로 하지 않는다. 또한 Maas의 직관적인 이중 balun설계 방법을 개선 EM simulation을 통한 이중 balun을 구성하는 방법을 제시하였다. 제안된 혼합기 회로는 CPW(Coplanar Waveguide)를 기반으로 하여 동국대 0.1 um GaAs pHEMT library를 이용 MMIC로 제작하였다. 제작된 혼합기는 크기 1.5 ${\times}$ 1.5 $\textrm{mm}^2$이며 DC bias로 성능 조정이 가능하다. 이것은 up/down converter로 사용 가능하며 V-band전역 이상의 주파수 대역폭을 갖고, 변환손실은 약 13∼18 ㏈ 정도이다.

• 한국전기전자재료학회논문지
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• 제21권4호
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• pp.311-320
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• 2008

In this paper, a 2.4 GHz low-voltage CMOS double-balanced down-conversion mixer using neutralization technique has been proposed and verified by circuit simulations and measurements. The grounded source structure was used for low-voltage operation. The neutralization technique was used to improve a conversion gain. The proposed mixer is fabricated in $0.25{\mu}m$ CMOS process for a 2.4 GHz wireless receiver. The mixer consumes 1.94 mW and gives conversion gain of 5.66 dB, input IP3 of 0.7 dBm and P1dB of -11.2 dBm at 1.5 V power supply. Measured results for the designed mixer show improved conversion gain of 2.86 dB over conventional mixer of grounded source structure.

• Journal of electromagnetic engineering and science
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• 제3권1호
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• pp.1-6
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• 2003

In this paper, a sub-harmonic dual-gate FET mixer is suggested to improve the isolation characteristic between LO and RF ports of an unbalanced mixer. The mixer was designed by using single-gate FET cascode structure and driven by the second harmonic component of LO signal. A dual-gate FET mixer has good isolation characteristic since RF and LO signals are injected into gatel and gate2, respectively. In addition, the isolation characteristic of a sub-harmonic mixer is better than that of a fundamental mixer due to the large frequency separation between the LO and RF frequencies. As RF power was -30 ㏈m and LO power was 0 ㏈m, the designed mixer yielded the -47.17 ㏈m LO-to-RF leakage power level, 10 ㏈ conversion gain, -2.5 ㏈m OIP3, -12.5 ㏈m IIP3 and -1 ㏈m 1 ㏈ gain compression point. Since the LO-to-RF leakage power level of the designed mixer is as good as that of a double-balanced mixer, the sub-harmonic dual-gate FET mixer can be utilized instead.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1508-1509
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• 2007

본 논문에서는 TSMC 0.18um공정을 이용한 무선통신 수신기용 직접변환 방식의 Double Balanced Mixer를 설계 하였다. 제안된 mixer는 current bleeding기법과 내부에 인덕터를 추가하여 기존의 Gilbert Cell구조의 mixer에 비해 변환 이득과 Flicker Noise특성을 향상 시켰다. 모의실험결과 2.45GHz에서 11dB의 변환이득을 나타내었으며 Flicker Noise의 corner frequency는 510kHz이고 이때 잡음특성은 10.8dB이다. 이 회로의 동작전압은 1.8V이며 소모 전력은 8.8mW이다.

• International journal of advanced smart convergence
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• 제10권3호
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• pp.81-88
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• 2021

This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.