• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.824-831
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• 2014

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.124-130
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• 2008

Automatic layout decomposition techniques have been developed for double patterning technology (DPT). As CMOS manufacturing process scales down to 45nm and below, lithography resolution needs to be improved. DPT has been proposed to enhance the limitation of conventional lithography, by decomposing the layout design into two masks to relax the minimum spacing requirement. However, it is not always possible to decompose a layout into two masks. We have developed new automatic stitching techniques to resolve this problem. Experimental results show that the suggested techniques are promising in decomposing layouts for DPT.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.11
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• pp.1256-1263
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• 2012

The present study covers the ultrasonic patterning process to replicate micro-patterns on a polymer substrate. The ultrasonic patterning process uses ultrasonic waves to generate frictional heat between an ultrasonic horn and the polymer substrate, from which the surface region of the polymer substrate is softened sufficiently for the replication of micro-patterns. The ultrasonic patterning process can divided into two categories according to the direction of vibration transmission: direct patterning and indirect patterning. The direct patterning uses a patterned horn, and the ultrasonic vibration is transferred directly from the patterned horn to the substrate. On the contrary, the indirect patterning process uses a plain horn, and the micro-patterns are engraved on a mold that is located below the substrate. Thus, the micro-patterns are replicated as an indirect manner. In this study, these direct and indirect patterning processes are compared in terms of the replication characteristics. Additionally, the possibility of double-side patterning is also discussed in comparison with the conventional single-side patterning process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.511-515
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• 2013

A Monte Carlo (MC) simulation study has been done in order to investigate the effects of line-edge-roughness (LER) induced by either 1P1E (single-patterning and single-etching) or 2P2E (double-patterning and double-etching) on fully-depleted silicon-on-insulator (FDSOI) tri-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Three parameters for characterizing the LER profile [i.e., root-mean square deviation (${\sigma}$), correlation length (${\zeta}$), and fractal dimension (D)] are extracted from the image-processed scanning electron microscopy (SEM) image for each photolithography method. It is experimentally verified that two parameters (i.e., ${\sigma}$ and D) are almost the same in each case, but the correlation length in the 2P2E case is longer than that in the 1P1E case. The 2P2E-LER-induced $V_TH$ variation in FDSOI tri-gate MOSFETs is smaller than the 1P1E-LER-induced $V_TH$ variation. The total random variation in $V_TH$, however, is very dependent on the other major random variation sources, such as random dopant fluctuation (RDF) and work-function variation (WFV).

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.436-437
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• 2012

Double patterning technology (DPT) has been suggested as a promising candidates of the next generation lithography technology in FLASH and DRAM manufacturing in sub-40nm technology node. DPT enables to overcome the physical limitation of optical lithography, and it is expected to be continued as long as e-beam lithography takes place in manufacturing. Several different processes for DPT are currently available in practice, and they are litho-litho-etch (LLE), litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and self-aligned double patterning (SADP) [1]. The self-aligned approach is regarded as more suitable for mass production, but it requires precise control of sidewall space etch profile for the exact definition of hard mask layer. In this paper, we propose etch end point detection (EPD) in spacer etching to precisely control sidewall profile in SADP. Conventional etch EPD notify the end point after or on-set of a layer being etched is removed, but the EPD in spacer etch should land-off exactly after surface removal while the spacer is still remained. Precise control of real-time in-situ EPD may help to control the size of spacer to realize desired pattern geometry. To demonstrate the capability of spacer-etch EPD, we fabricated metal line structure on silicon dioxide layer and spacer deposition layer with silicon nitride. While blanket etch of the spacer layer takes place in inductively coupled plasma-reactive ion etching (ICP-RIE), in-situ monitoring of plasma chemistry is performed using optical emission spectroscopy (OES), and the acquired data is stored in a local computer. Through offline analysis of the acquired OES data with respect to etch gas and by-product chemistry, a representative EPD time traces signal is derived. We found that the SE-EPD is useful for precise control of spacer etching in DPT, and we are continuously developing real-time SE-EPD methodology employing cumulative sum (CUSUM) control chart [2].

• Journal of the Korean Society of Costume
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• v.18
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• pp.97-110
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• 1992

West African's traditional looms, weaving and raw materials, structural patterning, dyeing and basic forms of dress were examines in the present study in order to deepen the appreciation of the cultural heritage of West Africa, and to make a contribution to the policy planning for export market developing The research method employed was the analysis f written materials. The study was limited to the traditional clothing habit which is preserved and practicing by them at the present day and the origin and the process of the historical development of those are not included in the scope of the present study. Followings are the results of the study: (1) They have vertical single-heddle loom horizontal or ground single-heddle loom, and double-heddle loom. The width of the cloth produced on the single-heddle loom varies about 38.5cm to 123cm and double-heddle looms all produced on the single-heddle looms all produced narrow strips of cloth varying in width from about 1.3cm to 75cm, although the average is about 10-20cm. (2) Despite the relative simplicity of the llom technology a remarkable variety of textiles are produced. (3) The most popular decorative technique in West African compound weaves is extra-weft patterning which is produced on both single-heddle and double-heddle loom by men and women weavers. Other forms of secondary patterning on textiles in West Africa are dyeing, applique, patchwork and embroidery. (4) Two basic forms of dress have spread throughout West Africa, the poncho (bpibpi) and the wrapper. Some versions of these basic forms are supplemented by western inspired trousers, shirts and blouses coupled with accessories usually complete their traditional outfits. They have a great variety of basic poncho, like as Khasa, Gandura, Tuareg-poncho, Babariga, Rigas (agba-da), Grand-boubou, Afteck, Tagua, buba, Danshike etc. Although West Africa has long been in contact with the peoples of the Nile region as well as the Maghreb and Sahara, both the boubou styles and the wrapper styles appear to have developed with a minimum of outside influence. African Islam was the principal agent for the diffusion of the boubou styles.

• Journal of Industrial and Engineering Chemistry
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• v.68
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• pp.293-300
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• 2018

Reduced graphene oxide (rGO) nanosheets were patterned with poly[benzodithiophene-bis(decyltetradecyl-thien) naphthothiadiazole] (PBDT-DTNT) and poly[bis(triiso-propylsilylethynyl) benzodithiophene-bis(decyltetradecyl-thien) naphthobisthiadiazole] (PBDT-TIPS-DTNT-DT) and used in photovoltaics. Conductive patternings changed via surface modification of rGO; because polymers encountered a high hindrance while assembling onto grafted rGO. The best records were detected in indium tin oxide (ITO):poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS):PBDTDTNT/rGO:PBDT-DTNT:LiF:Al devices, i.e., short current density $(J_{sc})=11.18mA/cm^2$, open circuit voltage $(V_{oc})=0.67V$, fill factor (FF) = 62% and power conversion efficiency (PCE) = 4.64%. PCE increased 2.31 folds after incorporation of PBDT-DTNT into thin films. Larger polymer assemblies on bared-rGO nanosheets resulted in greater phase separations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.12
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• pp.11-20
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• 1999

We have designed and fabricated direct-and gap-coupled microstrip hairpin-comb filters by patterning double-sided YBCO films on a single 50-mm-diameter, 0.5-mm-thick $LaAlO_3$ wafer. Both filters have a center frequency at 1.773 GHz, 12 MHz bandwidth, 0.5 dB minimum insertion loss in the passband, and very strong out-of- band rejection. Due to two attenuation poles below and above the passband, the direct-coupled hairpin-comb filter showed a better skirt characteristic than the gapcoupled hairpin-comb filter which had only one attenuation pole below the passband.