• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.313-321
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• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.4
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• pp.37-42
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• 1984

In this paper, effective methods of symbol timing in a 9600 bps modem are presented. The symbol timing circuit consists of a square-low device followed by a high-Q narrow band-pass filter tuned to a symbol frequency. Also, the advantages of using a digital phase-tooted loop (DPLL) to suppress side tones are described, and statistical properties of timing wave are derived. In addition, the overall performances of the symbol timing circuit are verified by computer simulation.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.410-415
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• 2014

This paper presents a new rectifier with a bootstrapping technique to reduce the effective drop voltage. An all-digital delay locked loop (ADDLL) circuit was also applied to prevent the reverse leakage current. The proposed rectifier uses NMOS diode connected instead of PMOS to reduce the design size and improve the frequency respond. All the sub-circuits of ADDLL were designed with low power consumption to reduce the total power of the rectifier. The rectifier was implemented in CMOS $0.35{\mu}m$ technology. The peak power conversion efficiency was 76 % at an input frequency of 6.78MHz and a power level of 5W.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.266-273
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• 2000

A frequency model of an OCXO (Oven Controlled X-tal Oscillator) is suggested to implement a holdover algorithm in a DP-PLL (Digital Processing-Phase Locked Loop) system. This model is presented simply with second order polynomials with respect to temperature and aging of the OCXO. The model parameters are obtained from experimental data by applying the LSM (Least Squared Method). A holdover algorithm is also suggest using the frequency model. The obtained model is verified to simulate the holdover algorithm with experimental phase data due to variation of temperature.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1994.10a
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• pp.499-503
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• 1994

The feedback control systems of welding process using visual information can improve weld qualities. However, it is very difficult to get the visual information of weld pool since welding are is much stronger than light from weld pool. To explore the possibility of extending the capability of automatic welding machines a study of a closed loop controlled welding system consisted of a GTA welding machine, a vision system, a stepping motor system and a digital computer was undertaken. Particularly, in this system, a CCD camera with 850nm long pass filter was focused on the weld pool to give a weld pool image. Subsequently, image analysis technique has been developed to measure a weld pool width. Using this weld pool width measurement, a colsed loop control system adjusted welding speed to maintain constant weld pool width.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.7
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• pp.9-15
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• 1999

In this paper, we propose a bit synchronizer which is suitable for frequency hopping systems. The proposed bit synchronizer is an ADPLL in which the digital loop filter is combined with an error symbol detecting circuit. Suppressing the tracking process, when hop mute and impulse noises are detected, improves the performance of the digital loop filter and enhances the probability of the frequency hopping system. Simulation results demonstrate an improved performance of the proposed bit synchronizer compared with existing ones.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1998.10a
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• pp.187-190
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• 1998

The values of physical components of the plants and controllers as well as the relevant environmental conditions change in time, thus the output performance can be deteriorated during the operating span of the system. Naturally the duty of calibration or the prevention of performance deterioration due to excessive component sensitivity should be provided to the control system. The proposed controller, whenever necessary, measures the open-loop and close-loop characteristics, and then calculates the offset and sensor gain correction values based on the prepared standard measurements It is applied to the control of a flexible link system with the gain and offset calibration problems in the light sensor module for position to show the applicability. In this paper, we propose a digital controller which has the capability of calibration gain and offset adjustment using fuzzy methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.5
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• pp.990-1006
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• 1997

This paper describes an interface function and its performance assessment for high-bit-rate digital subscriber line (HDSL) under ATM. The interface of HDSL function of ATM system was achieved by HDSL subscriber physical layer board assembly(HSPA) which was modeled as design standard for ATM. We have presented a new worst case of subscriber line conditions from existing results of investigations on impairments such as crosstalk, impulse noise, longitudinal, power line noise and others. We have measured the maximum service loop length available by HDSL, and found that HSPA, at a 2.048Mbps data transmission, is possible within a carrier serving area(CSA) under the worst case loop noise conditions at an error rate or 10$^{-7}$ on a two coordinated unshielded twisted pairs in the presense of impairments. We conclude tht, in terms of a performance-per-lin simulator, the HSPA is an excellent candidate for HDSL implementation under ATM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.506-514
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• 1997

In this paper, we implement digital circuit of despreading delay lock loop for GPS receiver. The designed system consists of Epoch signal generator, two 13bit correlators which correlates the received C/A code and the locally generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock synthesizer which generates the clock of the C/A code generator to control the phase and clock rate, the clock controller, and the clock divider. The designed circuit has the function of the acquisition and tracking by the autocorrelation characteristics of Gold code. The controller generates each other control signals according to the correlation value. The designed circuit is simulated to verify the logic functional performance. By using the simulator STR-2770 that generates the virtual GPS signal, the deigned FPGA chip is verified the circuit performance.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.4
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• pp.246-255
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• 2000

This paper deals with a novel full digital control method of the three-phase PWM inverter for UPS. The voltage and current of output filter capacitor as state variables are the feedback control input. In addition, a double deadbeat control consisting of a d-q current minor loop and a d-q voltage major loop, both with precise decoupling, have been developed. The switching pulse width modulation based on SVM is adopted so that the capacitor current should be exactly equal to its reference current. In order to compensate the calculation time delay, the predictive control is achieved by the current·voltage observer. The load prediction is used to compensate the load disturbance by disturbance observer with deadbeat response. The experimental results show that the proposed system offers an output voltage with THD less than 2% at a full nonlinear load.