Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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A Frequency Model of OCXO for Holdover Mode of DP-PLL

DP-PLL의 Holdover 모드에 대한 OCXO의 주파수 모델

  • Han, Wook (Electronic & Information Engineering, Konkuk University) ;
  • Hwang, Jin-Kwon (Control & Instrumentation Engineering, Hankyong National University) ;
  • Kim, Yung-Kwon (Electronic & Information Engineering, Konkuk University)
  • 한욱 (건국대학교 대학원 전자공학과) ;
  • 황진권 (한경대학교 제어계측 공학과) ;
  • 김영권 (건국대학교 전자공학과)
  • Published : 2000.12.01
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Abstract

A frequency model of an OCXO (Oven Controlled X-tal Oscillator) is suggested to implement a holdover algorithm in a DP-PLL (Digital Processing-Phase Locked Loop) system. This model is presented simply with second order polynomials with respect to temperature and aging of the OCXO. The model parameters are obtained from experimental data by applying the LSM (Least Squared Method). A holdover algorithm is also suggest using the frequency model. The obtained model is verified to simulate the holdover algorithm with experimental phase data due to variation of temperature.

OCXO (Oven Controlled X-tal Oscillator)의 주파수 모델이 holdover 알고리즘을 DP-PLL (Digital Processing-Phase Locked Loop) 시스템에 적용하기 위해 제안되었다. 이 모델은 온도와 OCXO의 노화에 따라 2차 다항식으로 간단하게 표현된다. 모델 변수들은 LSM (Least Squared Method)을 적용한 실험 데이터로부터 얻어진다. holdover 알고리즘은 다른 실험 데이터를 사용한 동일한 모델로 모의실험 할 수 있다.

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References

  1. IEEE Trans. Commun. v.28 no.8 Synchronized clock for DMS-IOO family Munter, E.A.
  2. IEEE Trans. Commun. v.COM-31 no.12 Intelligent PLL using. digital processing for network synchronization Fukinuki, H.;Furukawa, I.
  3. Bell System Technical Journal v.60 no.6 No. 4 ESS: Network clock synchronization Metz, R.;Reible, E.L.;Wnchel, D.F.
  4. Phase Locked Loops: Design, Simulation and Applications Best, R.E.
  5. System Identification Soderstrom, T.;Stoica, P.