• Proceedings of the Korea Contents Association Conference
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• 2004.05a
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• pp.372-376
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• 2004

Digital memory circuits have been developed very fast according to the progress of semiconductor technology But It was very difficult to memorize a high frequency radio signal. Many years ago an analog loop was used for store of radio frequency signal, and the digital radio frequency memory was made to the development of wideband amplifier and high speed sampler. We present a design of wide-band DRFM using Johnson code and the simulation results with respect to the sampling speed. in this paper.

• Proceedings of the KSR Conference
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• 2000.05a
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• pp.368-375
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• 2000

For safety reason ATS(Automatic Train Stop) system is being used, which is a kind of communication system with a feedback amplifier and a transformer on the train and wayside coils. The coils are highly resonant LC circuits, also have very high Q(Quality) factors. The Q factors of wayside ATS coils are to be maintained high enough for the amplifier to operate reliably. In this paper a novel Q measurement system is proposed. The system measures the resonant frequency and the bandwidth of the ATS coils, by controlling the phase difference between the transformer and the coil using digital PLL(Phase Locked Loop). The overall configuration and algorithms of the proposed system and the digital PLL control schemes are presented in details. The experimental waveforms are shown to verify the system performances.

• Journal of IKEEE
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• v.19 no.2
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• pp.176-185
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• 2015

The study aims to a design hybrid frequency synthesizer in spectrum analyzer and to propose new techniques designed for evasion of in-band spurious. The study focuses on calculating the exact location of multiple phase locked loop of hybrid frequency synthesizer and spurious of direct digital synthesizer to evade in-band spurious outside of frequency range that the user wants to see and thereby simulating technique to improve input related spurious of spectrum analyzer for algorithm. The proposed technique is designed to calculate spurious evasion algorithm in central processing system when in-band spurious arises, and to move output frequency of DDS(direct digital synthesizer) into the place where no in-band spurious exists thereby improving performance of frequency synthesizer. The study used simulation and result representation to prove the effectiveness of the proposed technique.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.85-88
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• 2000

In order to resolve problems according to the phase error in QPSK demodulator of the digital communication systems. The demodulator requires carrier recovery loop which searches for the frequency and phase of the carrier. In this paper the complexity of implementation is reduced by the reduction into half of the number of the multiplier in filter structure of the conventional carrier recovery loop, and as the drawback of NCO of the conventional carrier recovery loop wastes a amount of power for the structure of lookup table , We designed the structure of combinational logic without the lookup table. In the comparison with dynamic power of the proposed NCO, the power of NCO with the lookup table is 175㎼, NCO with the proposed structure is 24.65㎼. As the result, it is recognized that about one eight of loss power is reduced. In the simulation of carrier recovery loop designed QPSK demodulator, it is known that the carrier phase is compensated.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.13 no.11
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• pp.860-867
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• 2003

This paper presents a systematic method measuring a velocity disturbance to design the robust seek loop system of optical disk drives. The velocity disturbance caused by the rotation of a disk has a greater influence on the performance of the seek control loop as the rotational speed increases. Thus, it needs to measure the extent of the velocity disturbance and design the seek control loop based on the measured data. The measurement method of the velocity disturbance is a real-time . method using a measurable velocity and a velocity controller output and is a robust method considering actuator uncertainties. The loop gain adjustment algorithm is introduced to compensate for the actuator uncertainties. The proposed method is implemented by an experimental digital system and is evaluated through an experiment.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.73-74
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• 2016

In this paper, a design method for a wideband square loop antenna for Digital TV applications is studied. The proposed loop antenna is a square loop antenna combined with circular sectors to connect with central feed points. The input reflection coefficient and gain characteristics of the proposed antenna are analyzed to match with the 75 ohm input impedance for DTV applications. The optimized antenna is designed on FR4 substrate, and it operates in the frequency band of 470-1,300 MHz for a VSWR < 2, which assures the operation in the DTV band(470-806 MHz).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.2
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• pp.293-305
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• 1994

In this paper the efficient channel models of the subscriber loops for the ISDN U-interface digital transmission are presented. Several configuration medels of the loop network are adopted from the CCITT recommendations, and various parameters specifying the physical dimensions are determined in accordance with the measurements of the loop characteristics of Korea. A typical loop interfacing circuit is applied at both ends of the loops and the overall transmissing circuit model is obtained. Based on this circuit model of transmission. 3 types of signal path models, related to transmission, echo, and near end crosstalk noise are defined and their transfer function are respectively derived as the channel models. As examples of the proposed channel models, numerical calculation has been performed for some loop configuration models and the channel responses are investigation in both domains of frequency and time. It is shown that various changes of the loop characteristics can well be explained in terms of the proposed models. And these models can efficiently be used for the simulation of the digital transmission over the subscriber loop.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.