• 제목/요약/키워드: Differential amplifier

검색결과 238건 처리시간 0.028초

차동 증폭회로를 적용한 축전지 잔존용량산정 (State of Charge Calculation Using a Differential Amplifier On the Batteries)

  • 조규판;문채주;김태곤;채성열;정문선;이경성
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2011년도 전력전자학술대회
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    • pp.557-558
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    • 2011
  • 전기자동차의 축전지 관리 시스템(BMS : Battery Management System)의 잔존용량(SOC : State Of Charge)산정에는 Ah 측정법, 비중측정법, 전압측정법 등이 있다. 기존 전압 측정법의 경우 측정 전압을 프로세서에서 직접 처리하기 때문에 축전지의 미세한 전압 변화를 측정하지 못하여 잔존 용량 산정시 세밀한 계산에 어려움이 따른다. 본 논문에서는 축전지의 전압 측정 시 프로세서 전단에 전압의 부분 증폭회로를 추가하여 축전지의 미세한 전압변화를 증폭하여 측정하는 방법을 제안 하였다. 니켈수소전지를 대상으로 실험한 결과 충전 중 기존 전압측정법은 1.431V, 1.436V, 1.441V가 측정 되었을 때의 잔존 용량은 84%로 일정하였다. 같은 전압변화에서 부분증폭회로를 적용한 충전전압은 1.4297V, 1.4303V ~ 1.4352V, 1.4358V로 측정 되었으며, 그에 따른 잔존용량은 84% ~ 85%로 기존 전압 측정법 보다 약 9 ~ 10배 정도 세밀하게 측정 되었다. 제안한 방법을 통한 실험으로 제안된 방법이 기존 전압 측정법보다 세밀한 전압 측정 및 SOC산정이 가능함을 확인 하였다.

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기준전극의 형상과 입력전극사이의 간격을 고려한 건식형 표면 근전위 센서 개발 (Development of Dry-type Surface Myoelectric Sensor for the Shape of the Reference Electrode and the Inter-Electrode Distance)

  • 최기원;최규하
    • 대한전기학회논문지:시스템및제어부문D
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    • 제55권12호
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    • pp.550-557
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    • 2006
  • This paper proposes a dry-type surface myoelectric sensor for the myoelectric hand prosthesis. The designed surface myoelectric sensor is composed of skin interface and processing circuits. The skin interface has one reference and two input electrodes, and the reference electrode is located in the center of two input electrodes. In this paper is proposed two types of sensors with the circle- and bar-shaped reference electrode, but all input electrodes are the bar-shaped. The metal material of the electrodes is the stainless steel (SUS440) that endures sweat and wet conditions. Considering the conduction velocity and the median frequency of the myoelectric signal, the inter-electrode distance (IED) between two input electrodes as 18mm, 20mm, and 22mm is selected. The signal processing circuit consists of a differential amplifier with a band pass filter, a band rejection filter for rejecting 60Hz power-line noise, amplifiers, and a mean absolute value(MAV) circuit. Using SUS440, six prototype skin interface with different reference electrode shape and IED is fabricated, and their output characteristics are evaluated by output signal obtained from the forearm of a healthy subject. The experimental results show that the skin interface with parallel bar shape and the 18mm IED has a good output characteristics. The fabricated dry-type surface myoelectric sensor is evaluated for the upper-limb amputee.

고속 전류 테스팅 구현을 위한 내장형 CMOS 전류 감지기 회로의 설계에 관한 연구 (A Study on the Design of Built-in Current Sensor for High-Speed Iddq Testing)

  • 김후성;박상원;홍승우;성만영
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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    • pp.1254-1257
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    • 2004
  • This paper presents a built-in current sensor(BICS) that can detect defects in CMOS integrated circuits through current testing technique - Iddq test. Current test has recently been known to a complementary testing method because traditional voltage test cannot cover all kinds of bridging defects. So BICS is widely used for current testing. but there are some critical issues - a performance degradation, low speed test, area overhead, etc. The proposed BICS has a two operating mode- normal mode and test mode. Those methods minimize the performance degradation in normal mode. We also used a current-mode differential amplifier that has a input as a current, so we can realize higher speed current testing. Furthermore, only using 10 MOSFETS and 3 inverters, area overhead can be reduced by 6.9%. The circuit is verified by HSPICE simulation with 0.25 urn CMOS process parameter.

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고성능 연산 증폭기의 설계 자동화 (Design Automation of High-Performance Operational Amplifiers)

  • 유상대
    • 센서학회지
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    • 제6권2호
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    • pp.145-154
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    • 1997
  • 회로 시뮬레이션과 국부적 탐색을 갖는 시뮬레이티드 아닐링을 사용한 새로운 탐색 전략에 기초하여 고성능 연산 증폭기의 설계 자동화를 위한 기법을 제안하였다. 임의의 연산 증폭기 구조와 성능 규격에 대해서, 이산 설계 변수들을 갖는 비용 함수의 이산 최적화를 통해 연산 증폭기의 설계가 이루어진다. 설계 시간의 단축을 위해서 전용 회로 시뮬레이터와 몇 가지 휴리스틱을 사용하였다. 스마트 센서와 10 비트 25 MS/s 파이프라인 A/D 변환기에 사용 가능한 저전력 고속 전차동 CMOS 연산 증폭기의 설계를 통해서, 제안된 기법을 사용하여 개발된 설계 도구는 적은 설계 지식과 설계 노력을 가지고 고성능 연산 증폭기를 설계하는데 사용될 수 있음을 보였다.

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한방용(韓方用) 맥파 검출시스템 (Radial Pulse Wave Detection system for the Korean Medicine)

  • 이호재;김진우;김흥오;박영배;허웅
    • 대한의용생체공학회:학술대회논문집
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    • 대한의용생체공학회 1991년도 추계학술대회
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    • pp.66-69
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    • 1991
  • This paper describes a design of transducer for non-invasively detecting pressure radial pulse wave in aterial system and a recording system that for the studing the aterial pulse diagnosis of korean traditional medicine. The mechanism of transducer is composed of sensing mechanism, pressure sensor, conditioning amplifier. The variation of radial pulse pressure in the sensing mechanism is converted to the electric signal by piezo-resistive pressure sensor and it converted to the digital signal after preprocessing via A/D converter. The converted signals inputed to the computer as data files and then it display to the monitor for waveform watching and this datas can be used as the aterial pulse diagnosis data. This system effectively detect non-differential radial pulse wave and we conside that if analizing the recorded radial pulse wave, compared each other, it can be helpful in quantify radial pulse wave diagonosis of the Korean traditional medicine.

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An Ultra-precision Electronic Clinometer for Measurement of Small Inclination Angles

  • Tan, Siew-Leng;Kataoka, Satoshi;Ishikawa, Tatsuya;Ito, So;Shimizu, Yuuki;Chen, Yuanliu;Gao, Wei;Nakagawa, Satoshi
    • 한국생산제조학회지
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    • 제23권6호
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    • pp.539-546
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    • 2014
  • This paper describes an ultra-precision electronic clinometer, which is based on the capacitive-based fluid type, for detection of small inclination angles. The main parts of the clinometer low-noise electronics are two capacitance measurement circuits for converting the capacitances of the capacitors of the clinometer into voltages, and a differential amplifier for obtaining the difference of the capacitances, which is proportional to the input inclination angle. A 16 bit analog to digital (AD) converter is also embedded into the same circuit board, whose output is sent to a PC via RS-232C, for achieving a small noise level down to tens of ${\mu}v$. A compensation method, which is referred to as the delay time method for shortening the stabilization time of the sensor was also discussed. Experimental results have shown the possibility of achieving a measurement resolution of $0.0001^{\circ}$ as well as the quick measurement with the delay time method.

A 1.2 V 12 b 60 MS/s CMOS Analog Front-End for Image Signal Processing Applications

  • Jeon, Young-Deuk;Cho, Young-Kyun;Nam, Jae-Won;Lee, Seung-Chul;Kwon, Jong-Kee
    • ETRI Journal
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    • 제31권6호
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    • pp.717-724
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    • 2009
  • This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

A High Swing Range, High Bandwidth CMOS PGA and ADC for IF QPSK Receiver Using 1.8V Supply

  • Lee, Woo-Yol;Lim, Jong-Chul;Park, Hee-Won;Hong, Kuk-Tae;Lee, Hyeong-Soo
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제5권4호
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    • pp.276-281
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    • 2005
  • This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.

초기 비결합된 수직빗살 전극형 정전 스캐너의 거동제어 (Feedback control for initially unengaged vertical comb type electrostatic scanner)

  • 이병렬;원종화;조진우;정희문;조용철;이진호;고영철
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.845-846
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    • 2006
  • In this paper, we describe a capacitive position sensing and motion control scheme of a MEMS scanner used for laser display application. The laser displays can be made by scanning laser beams much the same way a CRT scans electron beams. So the accuracy of the scanner motion determines the quality of the displayed image. The MEMS scanner under consideration is composed of electrostatic comb electrodes with initial gap and requires large driving voltage. Due to the under-damping and nonlinear driving characteristics, the scanner motion is subject to be an unwanted oscillation. For the linear scanner motion, we devise a differential charge amplifier and phase compensator. The experimental results show that the implemented feedback control system provides sufficient electrical damping and improves the dynamic performance of the scanner.

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94.8dB의 SNR을 갖는 1-bit 4차 고성능 델타-시그마 모듈레이터 설계 (Design of a 94.8dB SNR 1-bit 4th-order high-performance delta-sigma Modulator)

  • 최영길;노형동;변산호;이현태;강경식;노정진
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.507-508
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    • 2006
  • High performance delta-sigma modulator is developed for audio-codec applications(i.e.. 16-bit resolution at a 20kHz signal bandwidth). The modulator is realized with fully-differential switched capacitor integrators. All stages employ a single-stage folded-cascode amplifier. The presented delta-sigma modulator when clocked at 3.2MHz achieves 85.2dB peak-SNDR and 94.8dB SNR. This modulator is designed in a SAMSUNG $0.18{\mu}m$ CMOS process. Finally, this paper shows the test setup and FFT result gained from delta-sigma modulator chip designed for audio applications.

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