• Title/Summary/Keyword: Difference Circuits

Search Result 146, Processing Time 0.023 seconds

Q Factor Measurement System for a ATS Coil Using Digital Phase Locked Loop (디지털 PLL을 이용한 ATS 지상자 코일 Q 측정장치 개발)

  • 김기택;임기택;최정용;김봉택
    • Proceedings of the KSR Conference
    • /
    • 2000.05a
    • /
    • pp.368-375
    • /
    • 2000
  • For safety reason ATS(Automatic Train Stop) system is being used, which is a kind of communication system with a feedback amplifier and a transformer on the train and wayside coils. The coils are highly resonant LC circuits, also have very high Q(Quality) factors. The Q factors of wayside ATS coils are to be maintained high enough for the amplifier to operate reliably. In this paper a novel Q measurement system is proposed. The system measures the resonant frequency and the bandwidth of the ATS coils, by controlling the phase difference between the transformer and the coil using digital PLL(Phase Locked Loop). The overall configuration and algorithms of the proposed system and the digital PLL control schemes are presented in details. The experimental waveforms are shown to verify the system performances.

  • PDF

A Simple Random Signal Generator Employing Current Mode Switched Capacitor Circuit

  • Yamakawa, Takeshi;Suetake, Noriaki;Miki, Tsutomu;Uchino, Eiji;Eguchi, Akihiro
    • Proceedings of the Korean Institute of Intelligent Systems Conference
    • /
    • 1993.06a
    • /
    • pp.865-868
    • /
    • 1993
  • This paper describes a simple random signal generator employing by CMOS analog technology in current mode. The system is a nonlinear dynamical system described by a difference equation, such as x(t+1) = f(x(t)) , t = 0,1,2, ... , where f($.$) is a nonlinear function of x(f). The tent map is used as a nonlinear function to produce the random signals with the uniform distribution. The prototype is implemented by using transistor array devices fabricated in a mass product line. It can be easily realized on a chip. Uniform randomness of the signal is examined by the serial correlation test and the $\chi$2 test.

  • PDF

The Implementation of Group Delay Equalizer and Its Performance Evaluation for Point-to-Point Digital Radio Relay System

  • Suh, Kyoung-Whoan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.11 no.8
    • /
    • pp.1444-1454
    • /
    • 2000
  • The implementation of IF group delay equalizer and its performance are presented for radio relay system applications, and measured results are in good agreement with the simulated ones based upon analytical formulations. For waveguide filter of 40㎒ channel spacing, equalized delay accuracy of about +/- 2.0nsec can be obtained only by constructing 4 stage delay circuits, which provides good performance in system BER curves compared with no filter case, and the difference is less than 1.0㏈ at $10^{-12}$ BER. So this scheme with simple hardware design can be used for correcting the distorted group delays mainly caused by wavegiude filters. To evaluate the designed group delay equalizer, various simulated and experimental results are shown here in conjunction with STM-1 signal of co-channel 64-QAM digital radio relay system.

  • PDF

Reduction of Heat Generation from Junction Box in 3 kW Photovoltaic Power Generation System

  • Yun, Jung-Hyun;Sun, Ki-Ju;Cheon, Min-Woo
    • Transactions on Electrical and Electronic Materials
    • /
    • v.17 no.1
    • /
    • pp.21-24
    • /
    • 2016
  • A junction box used in a 3 kW photovoltaic power generation system plays a role in collecting and supplying the direct current voltage produced by photovoltaic modules to an inverter. It is also used for facilitating maintenance checks and protecting the module and inverter by keeping the voltage constant. As for the junction box, using it in a parallel connection creates a difference between the setup modules. In order to compensate, an inverse voltage diode is used. But the high-power created through the solar generator can be delivered to the inverter through the inverter regularly. Therefore, a component can break down due to excess heat. And consequently short circuits and electric leakage occurs. In this study, using a junction box that enabled the bypass of high electric power, it was possible to reduce heat generation by approximately 35℃ when compared to a standard junction box.

Current Stimulator with Adaptive Supply Regulator for Artificial Retina Prosthesis (적응형 가변 전원 레귤레이터를 내장한 인공 망막용 전류 자극기)

  • Ko, Hyoung-Ho
    • Journal of Sensor Science and Technology
    • /
    • v.20 no.4
    • /
    • pp.254-259
    • /
    • 2011
  • In this paper, a current stimulator circuit with adaptive supply regulator for retinal prosthesis is proposed. In current stimulation systems, the stimulating circuits with wide voltage swing range are needed due to the high impedance of the retina cell and microelectrodes. Thus, previous researches adopt the high voltage architecture to obtain the enough operating range. The high voltage architecture, however, could increase the power consumption and can damage the retina cells. The proposed circuit provides the adaptively regulated supply voltage by measuring the difference between desired stimulation current and the actual stimulation current. The proposed circuit can achieve the extended range of the allowable cell impedance, improved accuracy of the stimulation current, and higher biosafety.

Quadrature Phase Detector for High Speed Delay-Locked Loop

  • Wang, Sung-Ho;Kim, Jung-tae;Hur, Chang-Wu
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2004.05a
    • /
    • pp.28-31
    • /
    • 2004
  • A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 urn standard CMOS process and it operates at 5 ㎓ frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

  • PDF

All Optical Logic Gates Based on Two Dimensional Plasmonic Waveguides with Nanodisk Resonators

  • Dolatabady, Alireza;Granpayeh, Nosrat
    • Journal of the Optical Society of Korea
    • /
    • v.16 no.4
    • /
    • pp.432-442
    • /
    • 2012
  • In this paper, we propose, analyze and simulate the performances of some new plasmonic logic gates in two dimensional plasmonic waveguides with nanodisk resonators, using the numerical method of finite difference time domain (FDTD). These gates, including XOR, XNOR, NAND, and NOT, can provide the highly integrated optical logic circuits. Also, by cascading and combining these basic logic gates, any logic operation can be realized. These devices can be utilized significantly in optical processing and telecommunication devices.

Power Supply-Insensitive Gbps Low Power LVDS I/O Circuits (공급 전압 변화에 둔감한 Gbps급 저전력 LVDS I/O회로)

  • Kim, Jae-Gon;Kim, Sam-Dong;Hwang, In-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.44 no.6 s.360
    • /
    • pp.19-27
    • /
    • 2007
  • This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.

Prevalence and Management of Venous Rupture Following Percutaneous Transluminal Angioplasty in Dysfunctional Arteriovenous Access: A Comparative Study of Primary Patency Rates with Non-Ruptured Access Circuits (동정맥루 기능 부전에서 경피적 혈관성형술 후 발생한 정맥 파열의 유병률 및 관리: 파열되지 않은 혈관과의 일차 개통 비교 연구)

  • Yoon Soo Park;Seung Boo Yang;Chae Hoon Kang;Dong Erk Goo
    • Journal of the Korean Society of Radiology
    • /
    • v.85 no.4
    • /
    • pp.746-753
    • /
    • 2024
  • Purpose This study aims to evaluate the incidence and management of venous ruptures after percutaneous transluminal angioplasty (PTA) for dysfunctional arteriovenous (AV) access. Materials and Methods From January 1998 to December 2015, 13506 PTA, mechanical thrombectomy, and thrombolysis procedures were performed in 6732 patients. The venous rupture rate following PTA was obtained, and access circuit primary patency (ACPP) was compared according to the etiology (PTA, thrombotic occlusion, and treatment type) of the venous rupture present. Results Venous rupture developed in 604 of the 13506 procedures. Venous ruptures were more frequent in female, AV graft cases, and in cases accompanied by thrombosis. Balloon tamponade was performed in 604 rupture cases, and stents were deployed in 119 cases where contrast extravasation and flow stasis persisted. ACPP was significantly better in the non-ruptured AV access circuits than in the ruptured group. However, AV access type and thrombosis was not associated with primary patency. In ruptured cases, ACPP is 8.4 months for prolonged balloon tamponade and 11.2 months for bare-metal stent insertion, showing statistically significant difference. Conclusion Balloon tamponade and bare-metal stent placement are effective treatment for PTA-induced venous ruptures. In particular, stent placement showed a similar ACPP to that of non-ruptured AV access circuits.

Simulations of Proposed Shallow Trench Isolation using TCAD Tool (TCAD 툴을 이용한 제안된 얕은 트랜치 격리의 시뮬레이션)

  • Lee, YongJae
    • Journal of the Korea Society for Simulation
    • /
    • v.22 no.4
    • /
    • pp.93-98
    • /
    • 2013
  • In this paper, the proposed shallow trench isolation structures for high threshold voltage for very large scale and ultra high voltage integrated circuits MOSFET were simulated. Physically based models of hot-carrier stress and dielectric enhanced field of thermal damage have been incorporated into a TCAD tool with the aim of investigating the electrical degradation in integrated devices over an extended range of stress biases and ambient temperatures. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.