• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.25-29
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• 2008

Reliability and performance in metal gate/high-k device with multiple gate dielectrics were investigated. MOSFETs with a thin $HfSiO_x$ layer on a thermal Si02 dielectric as gate dielectrics exhibit excellent mobility and low interface trap density. However, the distribution of threshold voltages of $HfSiO_x/SiO_2$ stack devices were wider than those of $SiO_2$ and $HfSiO_x$ single layer devices due to the penetration of Hf and/or intermixing of $HfSiO_x$ with underlying $SiO_2$. The results of TZDB and SILC characteristics suggested that a certain portion of $HfSiO_x$ layer reacted with the underlying thick $SiO_2$ layer, which in turn affected the reliability characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.335-338
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• 2003

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-layer dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding $1\;{\mu}m$ in size, which could cause micro-scratch on the wafer surface. In this paper, we have studied aging effect the of CMP sin as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.5
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• pp.351-355
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• 2001

Via for achieving reliable fabrication of MCM(Multichip Module) substrate was formed on photosensitive BCB layer. The MCM substrate consists of photosensitive BCB(Benzocyclobutene) interlayer dielectric and copper conductors. In order to form the vias in the photosensitive BCB layer, the process of forming the BCB layer and its via forming plasma etch using C$_2$F$\_$6//O$_2$ gas were evaluated. The thickness of the BCB layer after hard bake was shrunk down to 40% of the original. The resolution of vias formed on the BCB was 15㎛ and the slope after develop was 85 degree. AES analysis was done on two vias, one is etched in C$_2$F$\_$6/O$_2$ gas and the other isnot etched. On the via etched in C$_2$F$\_$6//O$_2$, native C was detected and the amount of native C was reduced after Ar sputter. On the via not etched in C$_2$F$\_$6//O$_2$, organic C was detected. As a result of AES, BCB residue was not removed by Ar sputter, so plasma etch is necessary for achieving reliable vias.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1546-1548
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• 2002

In this paper, the electrical characteristics of pentacene thin film transistors(TFTs) with stacked and surface-treated gate insulators have been investigated. The semiconductor layer of pentacene was thermally evaporated onto the stacked gate insulators. For the gate insulating materials. PVP(PolyvinylPhenol) and polystyrene were spin-coated with two different stacking orders, PVP-polystyrene and polystyrene-PVP. Rapid solvent evaporation during the spin-coating processes of these insulating layers produces non-equilibrium phase morphologies accompanied by surface undulations on gate insulator interfaces. This non-equilibrium phase morphology affects the growth mode of the subsequent pentacene layer. Therefore, in order to smoothen the gate dielectric surfaces, gate dielectric surfaces were rubbed laterally along the direction from the drain to the source TFTs with with stacked and surface-treated gate insulators have provided improved operational characteristics.

• Journal of the Korean Vacuum Society
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• v.13 no.3
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• pp.99-102
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• 2004

In this work the electrical characteristics of organic thin film transistors with the surface-treated organic gate insulator have been studied. For the surface treatment of gate dielectric, Ar plasma was used. Pentacene and PVP were used as active and dielectric layers respectively. Pentacene was thermally evaporated in vacuum at a pressure of about $10^{-6}$ Torr and at a deposition rate of 0.5 $\AA$/sec. PVP was spin coated and cured at $100^{\circ}C$. before pentacene deposition. organic thin film transistors with surface-treated gate insulators have provided improved operation characteristics.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.2
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• pp.98-102
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• 2000

Ferroelectric PZT heterolayered thin films were fabricated by spin coating method on the Pt/Ti/SiO2/Si substrate using PZT(10/90) and PZT(90/10) m7etal alkoxide solutions. All PZT heterolayered films showed a homogeneous grain structures without presence of rosette structure. It can be assumed that the lower PZT layers played a role of nucleation site for the formation of the upper PZT layer. Pb-deficient PZT phase was formed at PZT/Pt interface due to the diffusion of Pb element into a Pt bottom electrode. The relative dielectric constant and the dielectric loss of the PZT-6 film were 567 and 3.6%, respectively. Increasing the number of coatings, remanent polarization and coercive field were decreased and the values of the PZT-6 heterolayered film were $7.18\muC/cm^2$ and 68.5kV/cm, respectively. Leakage current densities were increased with increasing the number of coatings, and the value of the PZT-4 film was about $7\times10-8A/cm^2$ at 0.05MV/cm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1175-1180
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• 2003

Transformer Coupled Plasma Chemical Vapor Deposited (TCP-CVD) silicon nitride (SiNx) is widely used as a gate dielectric material for thin film transistors (TFT). This paper reports the SiNx films, grown by TCP-CVD at the low temperature (30$0^{\circ}C$). Experimental investigations were carried out for the optimization o(SiNx film as a function of $N_2$/SiH$_4$ flow ratio varying ,3 to 50 keeping rf power of 200 W, This paper presents the dielectric studies of SiNx gate in terms of deposition rate, hydrogen content, etch rate and leakage current density characteristics lot the thin film transistor applications. And also, this work investigated means to decrease the leakage current of SiNx film by employing $N_2$ plasma treatment. The insulator layers were prepared by two step process; the $N_2$ plasma treatment and then PECVD SiNx deposition with SiH$_4$, $N_2$gases.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.558-563
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• 1995

Dynamic characteristics of TbFeCo magneto-optical recording media at 680nm wavelength region were studied by means of computer simulation of disc structure and optimization of process variables during sputter deposition. With the slightly reduced Kerr rotation angle due to the reduced wavelength of optical laser source, the improved recording density in TbFeCo magneto optical media showing the CNR greater than 50dB could be achieved by only adjusting the thickness of dielectric and the recording layers when the wavelength of light source is changed from 780nm to 680nm. In addition, the recording power margin of 5mW and the 2mW minimum recording power was realized, It was shown from the present study that the increase in laser power density demonstrated feasibility of low cost and low power laser diode with the reduced optimum recording power.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.44 no.12
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• pp.1610-1616
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• 1995

The (Sr$_{1-x}$ .Ca$_{x}$)TiO$_{3}$(0.05.leq.x.leq.0.2) ceramics were fabricated to form semiconducting ceramics by sintering at about 1350[.deg. C] in a reducing atmosphere (N$_{2}$ gas). After being fired in a reducing atmosphere, metal oxides, CuO, was painted on the both surface of the specimens to diffuse to the grain boundary. They were annealed at 1100[.deg. C] for 2 hours. The 2nd phase formed by thermal diffusing from the surface lead to a very high apparent dielectric constant. The results of the capacitance-valtage measurements indicated that the grain boundary was composed of the continuous insulating layers. The capacitance is almost unchanged below about 20[V], but decreased slowly over 20[V]. The conduction mechanism of the specimens observed in the temperature range of 25~125[.deg. C], and is divided into three regions having different mechanism as the current increased: the region I below 200[V/cm] shows the ohmic conduction. The region II between 200[V/cm] and 2000[V/cm] can be explained by the Poole-Frenkel emission theory, and the region III above 2000[V/cm] is dominated by the tunneling effect.ct.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.8
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• pp.609-615
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• 2011

This paper is studied for the improvement of the characteristics of gate oxide with 3-nm-thick gate oxide by deuterium ion implantation methode. Deuterium ions were implanted to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas to nitrogen was performed to remove the damage of D-implantation. We simulated the deuterium ion implantation to find the optimum condition by SRIM (stopping and range of ions in matter) tool. We got the optimum condition by the results of simulation. We compare the electrical characteristics of the optimum condition with others terms. We also analyzed the electrical characteristics to change the annealing conditions after deuterium ion implantation. The results of the analysis, the breakdown time of the gate oxide was prolonged in the optimum condition. And a variety of annealing, we realized the dielectric property that annealing is good at longer time. However, the high temperature is bad because of thermal stress.