• Journal of the Korean Electrochemical Society
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• v.17 no.3
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• pp.139-148
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• 2014

Electrochemical energy-storage devices such as batteries and supercapacitors are important components in emerging portable electronic device, electric vehicle, and clean energy storage and supply technologies. This review describes recent progress in the development of nanostructured electrodes, the main component of the electrochemical energy-storage device, prepared by layer-by-layer (LbL) electrostatic assembly. Major advantages associated with, and challenges to, the fabrication of LbL electrodes, as well as the future outlook for expanding the application of LbL techniques, are discussed.

• Journal of the Semiconductor & Display Technology
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• v.5 no.4 s.17
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• pp.29-34
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• 2006

In order to design an OLED(Organic Luminescent Emitting Device) evaporation system, geometric simulation of film thickness distribution profile is required. For the OLED evaporation process, thin film thickness uniformity is of great practical importance. In this paper, a geometric modeling algorithm is introduced for process simulation of the OLED evaporating process. The physical fact of the evaporating process is modeled mathematically. Based on the developed method, the thickness of the thin-film layer can be successfully controlled.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1047-1050
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• 2009

The two approaches to improve the stability of oxide TFTs are described. First approach is the optimization of device architecture including MIS structure and passivation layer using conventional InGaZnO semiconductor channel layer. Second approach is to develop the new kinds of oxide semiconductor materials, which is very robust and stable against the gate bias stress and thermal stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.456-460
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• 1997

As device sizes are scaled to submicron dimensions, planarization technology becomes increasing1y important, both during device fabrication and during formation of multilevel interconnects and wiring. Chemical Mechanical Polishing (CMP) has emerged recently as a new processing technique for achieving a high degree of planarization for submicron VLSI applications. This paper is presented the results of CMP process window characterization studies for 0.35 micron process with 6 metal layers.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.1
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• pp.67-72
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• 1987

InSb TFT is fabricated by the vacuum evaporation method and I-V characteristics are measured. Employing Davidon Fletcher-Powell algorithm, the device parameters are extracted. The current-voltage relations calculated by extracdted parameters are in good agreement with experimental results. It is found that optimization technique may be more simple and accurate than curve fitting method in device parameters extration.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.13 no.2
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• pp.8-14
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• 2014

Many kinds of robots and machines have been developed to replace human laborin industrial and medical fields, as well as domestic life. In these applications, the device sneed to obtain environmental data using diverse sensors. Among such sensors, the tactile sensor is important because of its ability to get information regarding surface texture and force through the use of mechanical contact. In this research, a simple tactile sensor was developed using the direct writing of pressure sensitive material and layered fabrication of photocurable material. The body of the sensor was fabricated using layered fabrication, and pressure sensitive materials were dispensed between the layers using direct writing. We examined the line fabrication characteristics of the pressure sensitive material according to nozzle dispensing conditions. A simple $4{\times}4$ array flexible tactile sensor was successfully fabricated using the proposed process.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.322-325
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• 2005

The shrinking critical dimensions of modern technology place a heavy requirement on optimizing feature shapes at the micro- and nano scale. In addition, the use of ion beams in the nano-scale world is greatly increased by technology development. Especially, Focused ion Beam (FIB) has a great potential to fabricate the device in nano-scale. Nevertheless, FIB has several limitations, surface swelling in low ion dose regime, precipitation of incident ions, and the re-deposition effect due to the sputtered atoms. In recent years, many approaches and research results show that the re-deposition effect is the most outstanding effect to overcome or reduce in fabrication of micro and nano devices. A 2D string based simulation software AMADEUS-2D $(\underline{A}dvanced\;\underline{M}odeling\;and\;\underline{D}esign\;\underline{E}nvironment\;for\;\underline{S}putter\;Processes)$ for ion milling and FIB direct fabrication has been developed. It is capable of simulating ion beam sputtering and re-deposition. In this paper, the 2D FIB simulation is demonstrated and the characteristics of ion beam induced direct fabrication is analyzed according to various parameters. Several examples, single pixel, multi scan box region, and re-deposited sidewall formation, are given.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.30-37
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• 2006

In this article, we evaluated the structural merits and the validity of a partially insulated MOSFET (PiFET) through the fabrication of prototype transistors and an 80 nm 512M DDR DRAM with partially-insulated cell array transistors (PiCATs). The PiFETs showed the outstanding short channel effect immunity and off-current characteristics over the conventional MOSFET, resulting from self-induced halo region, self-limiting SID shallow junction, and reduced junction area due to PiOX layer formation. The DRAM with PiCATs also showed excellent data retention time. Thus, the PiFET can be a promising alternative for ultimate scaling of planar MOSFET.

• Journal of the Semiconductor & Display Technology
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• v.10 no.1
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• pp.63-73
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• 2011

Metamorphic HEMTs (MHEMTs) have emerged as excellent challenges for the design and fabrication of high-speed HEMTs for millimeter-wave applications. Some of improvements result from improved mobility and larger conduction band discontinuity in the channel, leading to more efficient modulation doping, better confinement, and better device performance compared with conventional pseudomorphic HEMTs (PHEMTs). For the optimized device design and development, we have performed the calibration on the DC characteristics of our fabricated 0.1 ${\mu}m$ ${\Gamma}$-gate MHEMT device having the modulation-doped $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}$As heterostructure on the GaAs wafer using the hydrodynamic transport model of a commercial 2D ISE-DESSIS device simulator. The well-calibrated device simulation shows very good agreement with the DC characteristic of the 0.1 ${\mu}m$ ${\Gamma}$-gate MHEMT device. We expect that our calibration result can help design over-100-GHz MHEMT devices for better device performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.15-19
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• 2001

Current leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaks and gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.